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1 omap35 15/03 applications processor 1.1 features omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 112k-byte rom omap35 15/03 applications processor: ? omap? 3 architecture 64k-byte shared sram ? mpu subsystem endianess: 600-mhz arm cortex?-a8 core ? arm instructions - little endian neon? simd coprocessor ? arm data ? configurable ? 2d/3d graphics accelerator (omap35 15 external memory interfaces: device only) ? sdram controller (sdrc) tile based architecture delivering up to 16, 32-bit memory controller with 10 mpoly/sec 1g-byte total address space universal scalable shader engine: interfaces to low-power double data multi-threaded engine incorporating rate (lpddr) sdram pixel and vertex shader functionality sdram memory scheduler (sms) and industry standard api support: rotation engine opengles 1.1 and 2.0, openvg1.0 and ? general purpose memory controller direct3d mobile (gpmc) fine grained task switching, load 16-bit wide multiplexed address/data balancing, and power management bus programmable high quality image up to 8 chip select pins with 128m-byte anti-aliasing address space per chip select pin ? fully software-compatible with arm9? glueless interface to nor flash, nand ? commercial and extended temperature flash (with ecc hamming code grades calculation), sram and pseudo-sram arm cortex?-a8 core flexible asynchronous protocol control ? armv7 architecture for interface to custom logic (fpga, trust zone? cpld, asics, etc.) thumb?-2 nonmultiplexed address/data mode (limited 2k-byte address space) mmu enhancements system direct memory access (sdma) ? in-order, dual-issue, superscalar microprocessor core controller (32 logical channels with ? neon? multimedia architecture configurable priority) ? over 2x performance of armv6 simd camera image signal processing (isp) ? supports both integer and floating point ? ccd and cmos imager interface simd ? memory data input ? jazelle? rct execution environment ? raw data interface architecture ? bt.601/bt.656 digital ycbcr 4:2:2 ? dynamic branch prediction with branch (8-/16-bit) interface target address cache, global history ? a-law compression and decompression buffer, and 8-entry return stack ? preview engine for real-time image ? embedded trace macrocell (etm) support processing for non-invasive debug ? glueless interface to common video arm cortex?-a8 memory architecture: decoders ? 16k-byte instruction cache (4-way ? histogram module/auto-exposure, set-associative) auto-white balance, and auto-focus ? 16k-byte data cache (4-way engine set-associative) ? resize engine ? 256k-byte l2 cache please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this document. is a trademark of ~ texas instruments. all other trademarks are the property of their respective owners. product preview information concerns products in the copyright ? 2008?2008, texas instruments incorporated formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com resize images from 1/4x to 4x digital (sd) with secure data i/o (sdio) separate horizontal/vertical control comprehensive power, reset, and clock management display subsystem ? smartreflex? technology ? parallel digital output ? dynamic voltage and frequency scaling up to 24-bit rgb (dvfs) hd maximum resolution test interfaces supports up to 2 lcd panels ? ieee-1149.1 (jtag) boundary-scan support for remote frame buffer compatible interface (rfbi) lcd panels ? embedded trace macro interface (etm) ? 2 10-bit digital-to-analog converters (dacs) supporting: ? serial data transport interface (sdti) composite ntsc/pal video 12 32-bit general purpose timers luma/chroma separate video (s-video) 2 32-bit watchdog timers ? rotation 90-, 180-, and 270-degrees 1 32-bit 32-khz sync timer ? resize images from 1/4x to 8x up to 188 general-purpose i/o (gpio) pins ? color space converter (multiplexed with other device functions) ? 8-bit alpha blending 65-nm cmos technology serial communication package-on-package (pop) implementation ? 5 multichannel buffered serial ports for memory stacking (not available in cus (mcbsps) package) 512 byte transmit/receive buffer discrete memory interface (not available in (mcbsp1/3/4/5) cbc package) 5k-byte transmit/receive buffer (mcbsp2) packages: sidetone core support (mcbsp2 and 3 ? 515-pin pbga package (cbb suffix), .5mm only) for filter, gain, and mix ball pitch (top), .4mm ball pitch (bottom) operations ? 515-pin s-pbga package (cbc suffix), direct interface to i2s and pcm device .65mm ball pitch (top), .5mm ball pitch and tdm buses (bottom) 128 channel transmit/receive mode ? 423-pin pbga package (cus suffix), .65mm ball pitch ? four master/slave multichannel serial port interface (mcspi) ports 1.8-v i/o and 3.0-v (mmc1 only), 0.8-v to ? high-speed/full-speed/low-speed usb 1.35-v adaptive processor core voltage, otg subsystem (12-/8-pin ulpi interface) 0.8-v to 1.15-v adaptive core logic voltage ? high-speed/full-speed/low-speed applications: multiport usb host subsystem ? portable navigation devices 12-/8-pin ulpi interface or 6-/4-/3-pin ? portable media player serial interface ? advanced portable consumer electronics supports transceiverless link logic ? digital tv (tll) ? digital video camera ? one hdq/1-wire interface ? portable data collection ? three uarts (one with infrared data ? point-of-sale devices association [irda] and consumer infrared [cir] modes) ? gaming ? three master/slave high-speed ? web tablet inter-integrated circuit (i2c) controllers ? smart white goods removable media interfaces: ? smart home controllers ? three multimedia card (mmc)/ secure ? ultra mobile devices omap35 15/03 applications processor 2 submit documentation feedback product preview
1.2 description omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 omap3515 and OMAP3503 high-performance, applications processors are based on the enhanced omap? 3 architecture. the omap? 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: streaming video 2d/3d mobile gaming video conferencing high-resolution still image video capture in 2.5g wireless terminals, 3g wireless terminals, and rich multimedia-featured handsets, and high-performance personal digital assistants (pdas). the device supports high-level operating systems (oss), such as: windows ce symbian os linux palm os this omap device includes state-of-the-art power-management techniques required for high-performance mobile products. the following subsystems are part of the device: microprocessor unit (mpu) subsystem based on the arm cortex?-a8 microprocessor sgx subsystem for 2d and 3d graphics acceleration to support display and gaming effects (35 15only) camera image signal processor (isp) that supports multiple formats and interfacing options connected to a wide variety of image sensors display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. the display subsystem also supports ntsc/pal video out. level 3 (l3) and level 4 (l4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals the device also offers: a comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. the device also supports smartreflex? adaptative voltage control. this power management technique for automatic control of the operating voltage of a module reduces the active power consumption. memory stacking feature using the package-on-package (pop) implementation (cbb and cbc packages only) omap 15/03 devices are available in a 515-pin pbga package (cbb suffix), 515-pin s-pbga package (cbc suffix), and a 423-pin pbga package (cus suffix). some features of the cbb and cbc packages are not available in the cus package. table 1-1 lists the differences between the cbb, cbc, and cus packages. submit documentation feedback omap35 15/03 applications processor 3 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 1-1. differences between cbb, cbc, and cus packages feature cbb package cbc package cus package for cbb package pin for cbc package pin for cus package pin pin assignments assignments seetable 2-1 , ball assignments see table 2-2 , ball assignments see table 2-3 , ball characteristics (cbb pkg.) characteristics (cbc pkg.) characteristics (cus pkg.) package-on-package (pop) pop interface supported pop interface supported pop interface not available interface discrete memory interface discrete memory interface not discrete memory interface discrete memory interface supported supported supported chip select pins gpmc_ncs1 and eight chip select pins available eight chip select pins available gpmc_ncs2 are not available gpmc wait pins gpmc_wait1 and four wait pins available four wait pins available gpmc_wait2 are not available cts signal is available on 3 pins the following signals are cts signal is available on 3 pins (triple muxed): uart2_cts (ag22 / available on one pin only: (triple muxed): uart2_cts (ac19 / uart1 w8 / t21), uart2_rts (ah22 / uart2_cts (ae21 / t19), uart2_rts ac2 / aa18), uart2_rts (w6 / aa9), uart2_tx (f28 / y8 / ae7), (ae22 / r2), uart2_tx (h3 / h25 / ab19), uart2_tx (e23 / v7 / ac3), uart2_rx (e26 / aa8) ae4), uart2_rx (l4 / g26) uart2_rx (d24 / w7) the following signals are the following signals are available on two pins (double the following signals are available on one pin only: muxed): uart2_cts (af6/ab26), available on one pin only: uart2 uart2_cts (y24), uart2_rts uart2_rts (ae6/ab25), uart2_tx uart2_cts (v6), uart2_rts (v5), (aa24), uart2_tx (ad22), (af5/aa25), uart2_rx uart2_tx (w4), uart2_rx (v4) uart2_rx (ad21) (ae5/ad25) the following signals are the following signals are the following signals are available on three pins (triple available on two pins (double available on two pins only muxed): mcbsp3_dx (af6 / ab26 muxed): mcbsp3_dx (u17/ y24), (double muxed): mcbsp3_dx mcbsp3 / v21), mcbsp3_dr (ae6 / ab25 / mcbsp3_dr (t20/ aa24), (tbd), mcbsp3_dr (tbd), u21), mcbsp3_clkx (af5 / aa25 / mcbsp3_clkx (t17/ ad22), mcbsp3_clkx (tbd), and w21), and mcbsp3_fsx (ae5 / mcbsp3_fsx (p20/ ad21) mcbsp3_fsx (tbd) ad25 / k26) the following signals are the following signals are the following signals are available on three pins (triple available on three pins (triple available on two pins only muxed): gpt8_pwm_evt (n8 / muxed): gpt8_pwm_evt (double muxed): gpt8_pwm_evt gp timer ad25 / v3), gpt9_pwm_evt (t8 / (c5/ad21/v9), gpt9_pwm_evt (tbd), gpt9_pwm_evt (tbd), ab26 / y2), gpt10_pwm_evt (r8 (b4/w8/y24), gpt10_pwm_evt (tbd), and / ab25 / y3), and gpt10_pwm_evt(c4/u8/aa24), gpt11_pwm_evt (tbd) gpt11_pwm_evt (p8 / aa25 / y4) gpt11_pwm_evt(b5/v8/ad22) the following signals are the following signals are the following signals are available on two pins (double available on one pin only: available on one pin only: muxed): mcbsp4_clkx (t8/ae1), mcbsp4 mcbsp4_clkx (b4), mcbsp4_dr mcbsp4_clkx (tbd), mcbsp4_dr mcbsp4_dr (r8/ad1), (c4), mcbsp4_dx (b5), (tbd), mcbsp4_dx (tbd), mcbsp4_dx (p8/ad2), mcbsp4_fsx (c5) mcbsp4_fsx (tbd) mcbsp4_fsx (n8/ac1) hsusb3_tll supported supported not supported mm_fsusb3 supported supported not supported four chip select pins are four chip select pins are chip select pins mcspi1_cs1 and mcspi1 available available mcspi_cs2 are not available the following signals are the following signals are the following signals are available on two pins (double available on two pins (double available on one pin only: mmc3 muxed): mmc3_cmd (ac3 / muxed): mmc3_cmd (r8 / ab3), mmc3_cmd (tbd), and ae10), and mmc3_clk (ab1 / mmc3_clk (r9 / ab2) mmc3_clk (tbd) af10) 4 omap35 15/03 applications processor submit documentation feedback product preview
1.3 functional block diagram omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 1-1. differences between cbb, cbc, and cus packages (continued) feature cbb package cbc package cus package a maximum of 170 gpio pins are supported. the following gpio pins are not available: gpio_112, gpio_113, gpio_114, gpio_115, gpio_52, gpio_53, gpio_63, gpio_64, gpio_144, gpio_145, gpio_146, a maximum of 188 gpio pins gpio tbd gpio_147, gpio_152, gpio_153, are supported. gpio_154, gpio_155, gpio_175, and gpio_176. pin muxing restricts the total number of gpio pins available at one time. for more details, see table 2-6 , multiplexing characteristics (cus pkg.). this omap35 15/03 applications processor data manual presents the electrical and mechanical specifications for the omap35 15/03 applications processor. the information contained in this data manual applies to both the commercial and extended temperature versions of the omap35 15/03 applications processor unless otherwise indicated. it consists of the following sections: a description of the omap35 15/03 terminals: assignment, electrical characteristics, multiplexing, and functional description (section 2 ) a presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics (section 3 ) the clock specifications: input and output clocks, dpll and dll (section 4 ) the video dac specification (section 5 ) the timing requirements and switching characteristics (ac timings) of the interfaces (section 6 ) a description of thermal characteristics, device nomenclature, and mechanical data about the available packaging (section 7 ) figure 1-1 shows the functional block diagram of the omap35 15/03 applications processor. submit documentation feedback omap35 15/03 applications processor 5 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 1-1. omap3515/03 functional block diagram 6 omap35 15/03 applications processor submit documentation feedback product preview 64 64 async 64 64 l2$ 256k mpu subsystem arm cortex- a8 tm core 16k/16k l1$ 2d/3d graphics accelerator (3515 only) 32 32 32 channel system dma 32 32 parallel tv amp lcd panel cvbs or s-video dual output 3-layer display processor (1xgraphics, 2xvideo) temporal dithering sdtv qcif support ? 32 camera isp image capture hardware image pipeline and preview dual- camera (serial and parallel) 64 hs usb host (with usb ttl) hs usb otg 32 l3 interconnect network-hierarchial, performance, and power driven 64k on-chip ram 2kb public/ 62kb secure 32 112k on-chip rom 80kb secure/ 32kb boot 32 sms: sdram memory scheduler/ rotation 64 sdrc: sdram memory controller l4 interconnect 32 system controls prcm 2xsmartreflex tm control module external peripherals interfaces peripherals: 3xuart, 3xhigh-speed i2c, 5xmcbsp (2x with sidetone/audio buffer) 4xmcspi, 6xgpio, 3xhigh-speed mmc/sdio, hdq/1 wire, 2xmailboxes 12xgptimers, 2xwdt, 32k sync timer gpmc: general purpose memory controller nand/ nor flash, sram 32 emulation debug: sdti, etm, jtag, coresight tm dap external and stacked memories 32 omap applications processor
contents omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 1 omap35 15/03 applications processor .............. 1 4.3 dpll and dll specifications ...................... 141 1.1 features .............................................. 1 5 video dac specifications ..................... 148 1.2 description ............................................ 3 5.1 interface description ............................... 148 5.2 electrical specifications over recommended 1.3 functional block diagram ............................ 5 operating conditions .............................. 150 revision history ............................................... 8 5.3 analog supply (vdda_dac) noise requirements .. 152 2 terminal description .............................. 9 5.4 external component value choice ................ 153 2.1 terminal assignment ................................. 9 6 timing requirements and switching 2.2 ball characteristics .................................. 14 characteristics .................................. 154 2.3 multiplexing characteristics ......................... 67 6.1 timing test conditions ............................ 154 2.4 signal description ................................... 90 6.2 interface clock specifications ..................... 154 3 electrical characteristics ................ 118 6.3 timing parameters ................................. 155 3.1 power domains .................................... 118 6.4 external memory interfaces ........................ 156 3.2 absolute maximum ratings ........................ 120 6.5 video interfaces .................................... 185 3.3 recommended operating conditions ............. 123 6.6 serial communications interfaces ................. 202 3.4 dc electrical characteristics ....................... 125 6.7 removable media interfaces ...................... 235 3.5 core voltage decoupling .......................... 128 6.8 test interfaces ..................................... 250 3.6 power-up and power-down ........................ 130 7 package characteristics .................... 256 4 clock specifications ........................... 133 7.1 package thermal resistance ...................... 256 4.1 input clock specifications ......................... 134 7.2 device support ..................................... 256 4.2 output clock specifications ........................ 139 submit documentation feedback contents 7 product preview
revision history omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com note: page numbers for previous revisions may differ from page numbers in the current version. this data manual revision history highlights the technical changes made to the sprs 505a device-specific data manual to make it an sprs 505b revision. see additions/modifications/deletions global added applicable updates for cbc package. table 2-1 updated/changed signal name from "vdds" to "vdds_mmc1a" for ball numbers p27, p26, r27, and r25. table 2-3 updated/changed signal name from "vdds" to "vdds_mmc1a" for ball numbers n22, n21, n20, and p24. section 2.4.1 updated/changed table 2-7 , external memory interfaces ? gpmc signals description section 2.4.3 updated/changed table 2-17 , serial communication interfaces ? mcbsp lp signals description section 2.4.3 updated/changed table 2-13 , serial communication interfaces ? usb signals description section 2.4.4 updated/changed table 2-20 , removable media interfaces ? mmc/sdio signals description section 2.4.8 updated/changed table 2-28 , system and miscellaneous signals description section 2.4.8 updated/changed table 2-28 , power supplies signals description section 3.2 updated/changed table 3-1 , absolute maximum ratings over operating junction temperature range section 3.3 updated/changed table 3-3 , recommended operating conditions section 3.4 updated/changed table 3-4 , dc electrical characteristics section 4.1.3 updated/changed table 4-5 , 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-mhz input clock squarer timing requirements section 4.2 updated/changed table 4-10 , sys_clkout1 output clock electrical characteristics and table 4-13 , sys_clkout2 output clock switching characteristics section 4.3.3 updated/changed table 4-14 , dpll characteristics 8 revision history submit documentation feedback product preview
2 terminal description 2.1 terminal assignment omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 2-1 , figure 2-2 , and figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array (pbga) packages. table 2-1 through table 2-29 indicate the signal names and ball grid numbers for both packages. note: there are no balls present on the top of the 423-ball pbga package. figure 2-1. omap35 15/03 applications processor cbb s-pbga-n515 package (bottom view) submit documentation feedback terminal description 9 product preview 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a b c d e f g h j k l m n p t r u v w y aa ab ac 24 25 26 27 28 ad ae af ag ah 1 030-001
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com balls a1, a2, a22, a23, ab1, ab2, ab22, ab23, ac1, ac2, ac22, ac23, b1, b2, b22, and b23 are unused. figure 2-2. omap35 15/03 applications processor cbb s-pbga-n515 package (top view) 10 terminal description submit documentation feedback product preview a c d e g k l m n p t r u v w y ab b f h j aa ac 22 21 20 18 17 16 15 13 12 10 9 8 7 6 5 4 3 2 1 11 14 19 23 030-002
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 2-3. omap35 15/03 applications processor cbc-sbga-515 package (bottom view) submit documentation feedback terminal description 11 product preview af ae adac ab aa y w v u t r p n m l k j h g f e dc b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 2-4. omap35 15/03 applications processor cbc-sbga-515 package (top view) 12 terminal description submit documentation feedback product preview aa y w v u t r p n m l k j h g f e dc b a 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 2-5. omap35 15/03 applications processor cus-pbga-n423 package (bottom view) submit documentation feedback terminal description 13 product preview ad ac ab aa y w v u t r p n m l k j h g f e d cb a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
2.2 ball characteristics omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1 through table 2-3 describe the terminal characteristics and the signals multiplexed on each pin for the cbb, cbc, and cus packages, respectively. the following list describes the table column headers. 1. ball bottom: ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. ball top: ball number(s) on the top side associated with each signal(s) on the top. 3. pin name: names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). note: table 2-1 through table 2-3 do not take into account subsystem pin multiplexing options. subsystem pin multiplexing options are described in section 2.4 , signal descriptions. 4. mode: multiplexing mode number. a. mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin corresponds to the name of the pin. there is always a function mapped on the primary mode. notice that primary mode is not necessarily the default mode. note: the default mode is the mode which is automatically configured on release of the internal global_pwron reset; also see the reset rel. mode column. b. modes 1 to 7 are possible modes for alternate functions. on each pin, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 5. type: signal direction ? i = input ? o = output ? i/o = input/output ? d = open drain ? ds = differential ? a = analog note: in the safe_mode, the buffer is configured in high-impedance. 6. ball reset state: the state of the terminal at reset (power up). ? 0: the buffer drives v ol (pulldown/pullup resistor not activated) 0(pd): the buffer drives v ol with an active pulldown resistor. ? 1: the buffer drives v oh (pulldown/pullup resistor not activated) 1(pu): the buffer drives v oh with an active pullup resistor. ? z: high-impedance ? l: high-impedance with an active pulldown resistor ? h : high-impedance with an active pullup resistor 7. ball reset rel. state: the state of the terminal at reset release. ? 0: the buffer drives v ol (pulldown/pullup resistor not activated) 0(pd): the buffer drives v ol with an active pulldown resistor. ? 1: the buffer drives v oh (pulldown/pullup resistor not activated) 1(pu): the buffer drives v oh with an active pullup resistor. ? z: high-impedance ? l: high-impedance with an active pulldown resistor ? h : high-impedance with an active pullup resistor 8. reset rel. mode: this mode is automatically configured on release of the internal global_pwron reset. 9. power: the voltage supply that powers the terminal?s i/o buffers. 10. hys: indicates if the input buffer is with hysteresis. 11. buffer strength: drive strength of the associated output buffer. 12. pull u/d - type: denotes the presence of an internal pullup or pulldown resistor. pullup and terminal description 14 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 pulldown resistors can be enabled or disabled via software. note: the pullup/pulldown drive strength is equal to 100 m a except for cbb balls p27, p26, r27, and r25 and cub balls n22, n21, n20, and p24, which the pulldown drive strength is equal to 1.8 k w . 13. io cell: io cell information. note: configuring two pins to the same input signal is not supported as it can yield unexpected results. this can be easily prevented with the proper software configuration. table 2-1. ball characteristics (cbb pkg.) (1) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] d6 j2 sdrc_d0 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c6 j1 sdrc_d1 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b6 g2 sdrc_d2 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c8 g1 sdrc_d3 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c9 f2 sdrc_d4 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a7 f1 sdrc_d5 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b9 d2 sdrc_d6 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a9 d1 sdrc_d7 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c14 b13 sdrc_d8 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b14 a13 sdrc_d9 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c15 b14 sdrc_d10 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b16 a14 sdrc_d11 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d17 b16 sdrc_d12 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c17 a16 sdrc_d13 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b17 b19 sdrc_d14 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d18 a19 sdrc_d15 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d11 b3 sdrc_d16 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b10 a3 sdrc_d17 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c11 b5 sdrc_d18 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d12 a5 sdrc_d19 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c12 b8 sdrc_d20 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a11 a8 sdrc_d21 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b13 b9 sdrc_d22 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d14 a9 sdrc_d23 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c18 b21 sdrc_d24 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a19 a21 sdrc_d25 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b19 d22 sdrc_d26 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b20 d23 sdrc_d27 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d20 e22 sdrc_d28 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a21 e23 sdrc_d29 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b21 g22 sdrc_d30 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c21 g23 sdrc_d31 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos h9 ab21 sdrc_ba0 0 o 0 0 0 vdds_ mem no 4 na lvcmos h10 ac21 sdrc_ba1 0 o 0 0 0 vdds_ mem no 4 na lvcmos a4 n22 sdrc_a0 0 o 0 0 0 vdds_ mem no 4 na lvcmos b4 n23 sdrc_a1 0 o 0 0 0 vdds_ mem no 4 na lvcmos b3 p22 sdrc_a2 0 o 0 0 0 vdds_ mem no 4 na lvcmos c5 p23 sdrc_a3 0 o 0 0 0 vdds_ mem no 4 na lvcmos c4 r22 sdrc_a4 0 o 0 0 0 vdds_ mem no 4 na lvcmos d5 r23 sdrc_a5 0 o 0 0 0 vdds_ mem no 4 na lvcmos c3 t22 sdrc_a6 0 o 0 0 0 vdds_ mem no 4 na lvcmos c2 t23 sdrc_a7 0 o 0 0 0 vdds_ mem no 4 na lvcmos c1 u22 sdrc_a8 0 o 0 0 0 vdds_ mem no 4 na lvcmos d4 u23 sdrc_a9 0 o 0 0 0 vdds_ mem no 4 na lvcmos (1) na in this table stands for not applicable. submit documentation feedback terminal description 15 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] d3 v22 sdrc_a10 0 o 0 0 0 vdds_ mem no 4 na lvcmos d2 v23 sdrc_a11 0 o 0 0 0 vdds_ mem no 4 na lvcmos d1 w22 sdrc_a12 0 o 0 0 0 vdds_ mem no 4 na lvcmos e2 w23 sdrc_a13 0 o 0 0 0 vdds_ mem no 4 na lvcmos e1 y22 sdrc_a14 0 o 0 0 0 vdds_ mem no 4 na lvcmos h11 m22 sdrc_ncs0 0 o 1 1 0 vdds_ mem no 4 na lvcmos h12 m23 sdrc_ncs1 0 o 1 1 0 vdds_ mem no 4 na lvcmos a13 a11 sdrc_clk 0 io l 0 0 vdds_ mem yes 4 pu/ pd lvcmos a14 b11 sdrc_nclk 0 o 1 1 0 vdds_ mem no 4 na lvcmos h16 j22 sdrc_cke0 0 o h 1 7 vdds_ mem yes 4 pu/ pd lvcmos safe_mode 7 h17 j23 sdrc_cke1 0 o h 1 7 vdds_ mem yes 4 pu/ pd lvcmos safe_mode 7 h14 l23 sdrc_nras 0 o 1 1 0 vdds_ mem no 4 na lvcmos h13 l22 sdrc_ncas 0 o 1 1 0 vdds_ mem no 4 na lvcmos h15 k23 sdrc_nwe 0 o 1 1 0 vdds_ mem no 4 na lvcmos b7 c1 sdrc_dm0 0 o 0 0 0 vdds_ mem no 4 na lvcmos a16 a17 sdrc_dm1 0 o 0 0 0 vdds_ mem no 4 na lvcmos b11 a6 sdrc_dm2 0 o 0 0 0 vdds_ mem no 4 na lvcmos c20 a20 sdrc_dm3 0 o 0 0 0 vdds_ mem no 4 na lvcmos a6 c2 sdrc_dqs0 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a17 b17 sdrc_dqs1 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a10 b6 sdrc_dqs2 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a20 b20 sdrc_dqs3 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos n4 ac15 gpmc_a1 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_34 4 io safe_mode 7 m4 ab15 gpmc_a2 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_35 4 io safe_mode 7 l4 ac16 gpmc_a3 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_36 4 io safe_mode 7 k4 ab16 gpmc_a4 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_37 4 io safe_mode 7 t3 ac17 gpmc_a5 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_38 4 io safe_mode 7 r3 ab17 gpmc_a6 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_39 4 io safe_mode 7 n3 ac18 gpmc_a7 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_40 4 io safe_mode 7 m3 ab18 gpmc_a8 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_41 4 io safe_mode 7 l3 ac19 gpmc_a9 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq2 1 i gpio_42 4 io safe_mode 7 k3 ab19 gpmc_a10 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq3 1 i terminal description 16 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] gpio_43 4 io safe_mode 7 k1 m2 gpmc_d0 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos l1 m1 gpmc_d1 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos l2 n2 gpmc_d2 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos p2 n1 gpmc_d3 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos t1 r2 gpmc_d4 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos v1 r1 gpmc_d5 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos v2 t2 gpmc_d6 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos w2 t1 gpmc_d7 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos h2 ab3 gpmc_d8 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_44 4 io safe_mode 7 k2 ac3 gpmc_d9 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_45 4 io safe_mode 7 p1 ab4 gpmc_d10 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_46 4 io safe_mode 7 r1 ac4 gpmc_d11 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_47 4 io safe_mode 7 r2 ab6 gpmc_d12 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_48 4 io safe_mode 7 t2 ac6 gpmc_d13 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_49 4 io safe_mode 7 w1 ab7 gpmc_d14 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_50 4 io safe_mode 7 y1 ac7 gpmc_d15 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_51 4 io safe_mode 7 g4 y2 gpmc_ncs0 0 o 1 1 0 vdds_ mem no 4 na lvcmos h3 y1 gpmc_ncs1 0 o h 1 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_52 4 io safe_mode 7 v8 na gpmc_ncs2 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_53 4 io safe_mode 7 u8 na gpmc_ncs3 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq0 1 i gpio_54 4 io safe_mode 7 t8 na gpmc_ncs4 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq1 1 i mcbsp4_ clkx 2 io gpt9_pwm_evt 3 io gpio_55 4 io safe_mode 7 r8 na gpmc_ncs5 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq2 1 i mcbsp4_dr 2 i submit documentation feedback terminal description 17 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] gpt10_pwm_evt 3 io gpio_56 4 io safe_mode 7 p8 na gpmc_ncs6 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq3 1 i mcbsp4_dx 2 io gpt11_pwm_evt 3 io gpio_57 4 io safe_mode 7 n8 na gpmc_ncs7 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt8_pwm_evt 3 io gpio_58 4 io safe_mode 7 t4 w2 gpmc_clk 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_59 4 io safe_mode 7 f3 w1 gpmc_nadv_ale 0 o 0 0 0 vdds_ mem no 4 na lvcmos g2 v2 gpmc_noe 0 o 1 1 0 vdds_ mem no 4 na lvcmos f4 v1 gpmc_nwe 0 o 1 1 0 vdds_ mem no 4 na lvcmos g3 ac12 gpmc_nbe0_cle 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_60 4 io safe_mode 7 u3 na gpmc_nbe1 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_61 4 io safe_mode 7 h1 ab10 gpmc_nwp 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_62 4 io safe_mode 7 m8 ab12 gpmc_wait0 0 i h h 0 vdds_ mem yes na pu/ pd lvcmos l8 ac10 gpmc_wait1 0 i h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_63 4 io safe_mode 7 k8 na gpmc_wait2 0 i h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_64 4 io safe_mode 7 j8 na gpmc_wait3 0 i h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq1 1 i gpio_65 4 io safe_mode 7 d28 na dss_pclk 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_66 4 io safe_mode 7 d26 na dss_hsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_67 4 io safe_mode 7 d27 na dss_vsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_68 4 io safe_mode 7 e27 na dss_acbias 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_69 4 io safe_mode 7 ag22 na dss_data0 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos terminal description 18 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] uart1_cts 2 i gpio_70 4 io safe_mode 7 ah22 na dss_data1 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart1_rts 2 o gpio_71 4 io safe_mode 7 ag23 na dss_data2 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos gpio_72 4 io safe_mode 7 ah23 na dss_data3 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos gpio_73 4 io safe_mode 7 ag24 na dss_data4 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart3_rx_ irrx 2 i gpio_74 4 io safe_mode 7 ah24 na dss_data5 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart3_tx_ irtx 2 o gpio_75 4 io safe_mode 7 e26 na dss_data6 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_tx 2 o gpio_76 4 io safe_mode 7 f28 na dss_data7 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rx 2 i gpio_77 4 io safe_mode 7 f27 na dss_data8 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_78 4 io safe_mode 7 g26 na dss_data9 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_79 4 io safe_mode 7 ad28 na dss_data10 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_80 4 io safe_mode 7 ad27 na dss_data11 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_81 4 io safe_mode 7 ab28 na dss_data12 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_82 4 io safe_mode 7 ab27 na dss_data13 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_83 4 io safe_mode 7 aa28 na dss_data14 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_84 4 io safe_mode 7 aa27 na dss_data15 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_85 4 io safe_mode 7 submit documentation feedback terminal description 19 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] g25 na dss_data16 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_86 4 io safe_mode 7 h27 na dss_data17 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_87 4 io safe_mode 7 h26 na dss_data18 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 h25 na dss_data19 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_ simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 e28 na dss_data20 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 j26 na dss_data21 0 o l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 ac27 na dss_data22 0 o l l 7 vdds na 4 pu/ pd lvds/ cmos mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 ac28 na dss_data23 0 o l l 7 vdds na 4 pu/ pd lvds/ cmos dss_data5 3 io gpio_93 4 io safe_mode 7 w28 na tv_out2 0 o z 0 0 vddadac 8 na 10-bit dac y28 na tv_out1 0 o z 0 0 vddadac 8 na 10-bit dac y27 na tv_vfb1 0 o z na 0 vddadac na 10-bit dac w27 na tv_vfb2 0 o z na 0 vddadac na 10-bit dac w26 na tv_vref 0 i z na 0 vddadac na 10-bit dac a24 na cam_hs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_94 4 io safe_mode 7 a23 na cam_vs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_95 4 io safe_mode 7 c25 na cam_ xclka 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_96 4 io safe_mode 7 c27 na cam_pclk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_97 4 io safe_mode 7 c23 na cam_fld 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io terminal description 20 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] gpio_98 4 io safe_mode 7 ag17 na cam_d0 0 i l l 7 vdds yes 4 pd lvds/ cmos gpio_99 4 i safe_mode 7 ah17 na cam_d1 0 i l l 7 vdds yes 4 pd lvds/ cmos gpio_100 4 i safe_mode 7 b24 na cam_d2 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_101 4 io safe_mode 7 c24 na cam_d3 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_102 4 io safe_mode 7 d24 na cam_d4 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_103 4 io safe_mode 7 a25 na cam_d5 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_104 4 io safe_mode 7 k28 na cam_d6 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_105 4 io safe_mode 7 l28 na cam_d7 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_106 4 io safe_mode 7 k27 na cam_d8 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_107 4 io safe_mode 7 l27 na cam_d9 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_108 4 io safe_mode 7 b25 na cam_d10 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_109 4 io safe_mode 7 c26 na cam_d11 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_110 4 io safe_mode 7 b26 na cam_ xclkb 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_111 4 io safe_mode 7 b23 na cam_wen 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_167 4 io safe_mode 7 d25 na cam_ strobe 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_126 4 io safe_mode 7 ag19 na gpio_112 4 i l l 7 vdds yes 4 pd lvds/ cmos safe_mode 7 ah19 na gpio_113 4 i l l 7 vdds yes 4 pd lvds/ cmos safe_mode 7 ag18 na gpio_114 4 i l l 7 vdds yes 4 pd lvds/ cmos safe_mode 7 submit documentation feedback terminal description 21 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] ah18 na gpio_115 4 i l l 7 vdds yes 4 pd lvds/ cmos safe_mode 7 p21 na mcbsp2_fsx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_116 4 io safe_mode 7 n21 na mcbsp2_ clkx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_117 4 io safe_mode 7 r21 na mcbsp2_dr 0 i pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_118 4 io safe_mode 7 m21 na mcbsp2_dx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_119 4 io safe_mode 7 n28 na mmc1_clk 0 o l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_120 4 io safe_mode 7 m27 na mmc1_cmd 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_121 4 io safe_mode 7 n27 na mmc1_dat0 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_122 4 io safe_mode 7 n26 na mmc1_dat1 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_123 4 io safe_mode 7 n25 na mmc1_dat2 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_124 4 io safe_mode 7 p28 na mmc1_dat3 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_125 4 io safe_mode 7 p27 na mmc1_dat4 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_126 4 io safe_mode 7 p26 na mmc1_dat5 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_127 4 io safe_mode 7 r27 na mmc1_dat6 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_128 4 io safe_mode 7 r25 na mmc1_dat7 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_129 4 io safe_mode 7 ae2 na mmc2_clk 0 o l l 7 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io gpio_130 4 io safe_mode 7 ag5 na mmc2_ cmd 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io gpio_131 4 io safe_mode 7 (2) the buffer strength of this io cell is programmable (2, 4, 6, or 8 ma) according to the selected mode; the default value is described in the above table. terminal description 22 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] ah5 na mmc2_ dat0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io gpio_132 4 io safe_mode 7 ah4 na mmc2_ dat1 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_133 4 io safe_mode 7 ag4 na mmc2_ dat2 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 af4 na mmc2_ dat3 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 ae4 na mmc2_ dat4 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 ah3 na mmc2_ dat5 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io gpio_137 4 io hsusb3_tll_stp 5 io mm3_rxdp 6 io safe_mode 7 af3 na mmc2_ dat6 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_ cmd 1 o cam_ shutter 2 o mmc3_dat2 3 io gpio_138 4 io hsusb3_tll_dir 5 io safe_mode 7 ae3 na mmc2_ dat7 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_ clkin 1 i mmc3_dat3 3 io gpio_139 4 io hsusb3_tll_nxt 5 io mm3_rxdm 6 io safe_mode 7 af6 na mcbsp3_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_cts 1 i gpio_140 4 io hsusb3_tll_ data4 5 io safe_mode 7 ae6 na mcbsp3_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos uart2_rts 1 o gpio_141 4 io hsusb3_tll_ data5 5 io safe_mode 7 submit documentation feedback terminal description 23 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] af5 na mcbsp3_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_tx 1 o gpio_142 4 io hsusb3_tll_ data6 5 io safe_mode 7 ae5 na mcbsp3_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_rx 1 i gpio_143 4 io hsusb3_tll_ data7 5 io safe_mode 7 ab26 na uart2_cts 0 i h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_dx 1 io gpt9_pwm_evt 2 io gpio_144 4 io safe_mode 7 ab25 na uart2_rts 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_dr 1 i gpt10_pwm_evt 2 io gpio_145 4 io safe_mode 7 aa25 na uart2_tx 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_ clkx 1 io gpt11_pwm _evt 2 io gpio_146 4 io safe_mode 7 ad25 na uart2_rx 0 i h h 7 vdds yes 4 pu/ pd lvcmos mcbsp3_fsx 1 io gpt8_pwm_evt 2 io gpio_147 4 io safe_mode 7 aa8 na uart1_tx 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_148 4 io safe_mode 7 aa9 na uart1_rts 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_149 4 io safe_mode 7 w8 na uart1_cts 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_150 4 io hsusb3_tll_clk 5 o safe_mode 7 y8 na uart1_rx 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcbsp1_ clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 ae1 na mcbsp4_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_152 4 io hsusb3_tll_ data1 5 io mm3_txse0 6 io safe_mode 7 ad1 na mcbsp4_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_153 4 io hsusb3_tll_ data0 5 io mm3_rxrcv 6 io terminal description 24 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] safe_mode 7 ad2 na mcbsp4_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_154 4 io hsusb3_tll_ data2 5 io mm3_txdat 6 io safe_mode 7 ac1 na mcbsp4_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_155 4 io hsusb3_tll_ data3 5 io mm3_txen_n 6 io safe_mode 7 y21 na mcbsp1_ clkr 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_clk 1 io gpio_156 4 io safe_mode 7 aa21 na mcbsp1_fsr 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_157 4 io safe_mode 7 v21 na mcbsp1_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 u21 na mcbsp1_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ somi 1 io mcbsp3_dr 2 o gpio_159 4 io safe_mode 7 t21 na mcbsp_clks 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 k26 na mcbsp1_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io safe_mode 7 w21 na mcbsp1_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcbsp3_ clkx 2 io gpio_162 4 io safe_mode 7 h18 na uart3_cts_ rctx 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_163 4 io safe_mode 7 h19 na uart3_rts_ sd 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_164 4 io safe_mode 7 h20 na uart3_rx_ irrx 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_165 4 io safe_mode 7 h21 na uart3_tx_ irtx 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_166 4 io submit documentation feedback terminal description 25 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] safe_mode 7 t28 na hsusb0_clk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_120 4 io safe_mode 7 t25 na hsusb0_stp 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_121 4 io safe_mode 7 r28 na hsusb0_dir 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_122 4 io safe_mode 7 t26 na hsusb0_nxt 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_124 4 io safe_mode 7 t27 na hsusb0_ data0 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_tx_ irtx 2 o gpio_125 4 io safe_mode 7 u28 na hsusb0_ data1 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rx_ irrx 2 i gpio_130 4 io safe_mode 7 u27 na hsusb0_ data2 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rts_ sd 2 o gpio_131 4 io safe_mode 7 u26 na hsusb0_ data3 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_cts_ rctx 2 io gpio_169 4 io safe_mode 7 u25 na hsusb0_ data4 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_188 4 io safe_mode 7 v28 na hsusb0_ data5 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_189 4 io safe_mode 7 v27 na hsusb0_ data6 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_190 4 io safe_mode 7 v26 na hsusb0_ data7 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_191 4 io safe_mode 7 k21 na i2c1_scl 0 iod h h 0 vdds yes 4 pu/ pd open drain j21 na i2c1_sda 0 iod h h 0 vdds yes 4 pu/ pd open drain af15 na i2c2_scl 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_168 4 io safe_mode 7 ae15 na i2c2_sda 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_183 4 io safe_mode 7 af14 na i2c3_scl 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_184 4 io safe_mode 7 ag14 na i2c3_sda 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_185 4 io terminal description 26 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] safe_mode 7 ad26 na i2c4_scl 0 iod h h 0 vdds yes 4 pu/ pd open drain sys_ nvmode1 1 o safe_mode 7 ae26 na i2c4_sda 0 iod h h 0 vdds yes 4 pu/ pd open drain sys_ nvmode2 1 o safe_mode 7 j25 na hdq_sio 0 iod h h 7 vdds yes 4 pu/ pd lvcmos sys_altclk 1 i i2c2_sccbe 2 o i2c3_sccbe 3 o gpio_170 4 io safe_mode 7 ab3 na mcspi1_clk 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat4 1 io gpio_171 4 io safe_mode 7 ab4 na mcspi1_ simo 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat5 1 io gpio_172 4 io safe_mode 7 aa4 na mcspi1_ somi 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat6 1 io gpio_173 4 io safe_mode 7 ac2 na mcspi1_cs0 0 io pgm h 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat7 1 io gpio_174 4 io safe_mode 7 ac3 na mcspi1_cs1 0 o pgm h 7 vdds yes 4 (2) pu/ pd lvcmos mmc3_cmd 3 io gpio_175 4 io safe_mode 7 ab1 na mcspi1_cs2 0 o pgm h 7 vdds yes 4 (2) pu/ pd lvcmos mmc3_clk 3 o gpio_176 4 io safe_mode 7 ab2 na mcspi1_cs3 0 o h h 7 vdds yes 4 pu/ pd lvcmos hsusb2_tll_ data2 2 io hsusb2_ data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 aa3 na mcspi2_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos hsusb2_tll_ data7 2 io hsusb2_ data7 3 o gpio_178 4 io safe_mode 7 y2 na mcspi2_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt9_pwm_evt 1 io hsusb2_tll_ data4 2 io hsusb2_ data4 3 i gpio_179 4 io safe_mode 7 submit documentation feedback terminal description 27 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] y3 na mcspi2_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt10_pwm_evt 1 io hsusb2_tll_ data5 2 io hsusb2_ data5 3 o gpio_180 4 io safe_mode 7 y4 na mcspi2_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpt11_pwm_evt 1 io hsusb2_tll_ data6 2 io hsusb2_ data6 3 o gpio_181 4 io safe_mode 7 v3 na mcspi2_cs1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpt8_pwm_evt 1 io hsusb2_tll_ data3 2 io hsusb2_ data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 ae25 na sys_32k 0 i z i na vdds yes na na lvcmos ae17 na sys_xtalin 0 i z i na vdds yes na lvcmos af17 na sys_xtalout 0 o z o na vdds yes na lvcmos af25 na sys_clkreq 0 io 0 1 0 vdds yes 4 pu/ pd lvcmos gpio_1 4 io safe_mode 7 af26 na sys_nirq 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_0 4 io safe_mode 7 ah25 na sys_ nrespwron 0 i z i na vdds yes na na lvcmos af24 na sys_ nreswarm 0 iod 0 1 (pu) 0 vdds yes 4 pu/ pd lvcmos gpio_30 4 io safe_mode 7 ah26 na sys_boot0 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_2 4 io safe_mode 7 ag26 na sys_boot1 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_3 4 io safe_mode 7 ae14 na sys_boot2 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_4 4 io safe_mode 7 af18 na sys_boot3 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_5 4 io safe_mode 7 af19 na sys_boot4 0 i z z 0 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat2 1 o gpio_6 4 io safe_mode 7 ae21 na sys_boot5 0 i z z 0 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat3 1 o gpio_7 4 io safe_mode 7 af21 na sys_boot6 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_8 4 io terminal description 28 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] safe_mode 7 af22 na sys_off_ mode 0 o 0 l 7 vdds yes 4 pu/ pd lvcmos gpio_9 4 io safe_mode 7 ag25 na sys_clkout1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_10 4 io safe_mode 7 ae22 na sys_clkout2 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_186 4 io safe_mode 7 b1 na sys_ ipmcsws 0 ai z ai na vdds na na na analog a1 na sys_ opmcsws 0 ao 0 ao na vdds no na na lvcmos aa17 na jtag_ntrst 0 i l l 0 vdds yes na pu/ pd lvcmos aa13 na jtag_tck 0 i l l 0 vdds yes na pu/ pd lvcmos aa12 na jtag_rtck 0 o l 0 0 vdds yes 4 pu/ pd lvcmos aa18 na jtag_tms_tmsc 0 io h h 0 vdds yes 4 pu/ pd lvcmos aa20 na jtag_tdi 0 i h h 0 vdds yes na pu/ pd lvcmos aa19 na jtag_tdo 0 o l z 0 vdds yes 4 pu/ pd lvcmos aa11 na jtag_emu0 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_11 4 io safe_mode 7 aa10 na jtag_emu1 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_31 4 io safe_mode 7 af10 na etk_clk 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcbsp5_ clkx 1 io mmc3_clk 2 o hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hsusb1_tll_stp 6 i ae10 na etk_ctl 0 o h h 4 vdds yes 4 pu/ pd lvcmos mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io hsusb1_tll_clk 6 o af11 na etk_d0 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io mmc3_dat4 2 io hsusb1_ data0 3 io gpio_14 4 io mm1_rxrcv 5 io hsusb1_tll_ data0 6 io ag12 na etk_d1 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io hsusb1_ data1 3 io gpio_15 4 io mm1_txse0 5 io hsusb1_tll_ data1 6 io submit documentation feedback terminal description 29 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] ah12 na etk_d2 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io hsusb1_ data2 3 io gpio_16 4 io mm1_txdat 5 io hsusb1_tll_data2 6 io ae13 na etk_d3 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io mmc3_dat3 2 io hsusb1_ data7 3 io gpio_17 4 io hsusb1_tll_ data7 6 io ae11 na etk_d4 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_ data4 3 io gpio_18 4 io hsusb1_tll_ data4 6 io ah9 na etk_d5 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_ data5 3 io gpio_19 4 io hsusb1_tll_ data5 6 io af13 na etk_d6 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dx 1 io mmc3_dat2 2 io hsusb1_ data6 3 io gpio_20 4 io hsusb1_tll_ data6 6 io ah14 na etk_d7 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o mmc3_dat7 2 io hsusb1_ data3 3 io gpio_21 4 io mm1_txen_n 5 io hsusb1_tll_ data3 6 io af9 na etk_d8 0 o l l 4 vdds yes 4 pu/ pd lvcmos sys_drm_ 1 o msecure mmc3_dat6 2 io hsusb1_dir 3 i gpio_22 4 io hsusb1_tll_dir 6 o ag9 na etk_d9 0 o l l 4 vdds yes 4 pu/ pd lvcmos sys_secure_indic 1 o ator mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hsusb1_tll_nxt 6 o terminal description 30 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-1. ball characteristics (cbb pkg.) (continued) ball ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] top [2] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type state [7] [12] ae7 na etk_d10 0 o l l 4 vdds yes 4 pu/ pd lvcmos uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hsusb2_tll_clk 6 o af7 na etk_d11 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hsusb2_tll_stp 6 i ag7 na etk_d12 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_dir 3 i gpio_26 4 io hsusb2_tll_dir 6 o ah7 na etk_d13 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_nxt 3 i gpio_27 4 io mm2_rxdm 5 io hsusb2_tll_nxt 6 o ag8 na etk_d14 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data0 3 io gpio_28 4 io mm2_rxrcv 5 io hsusb2_tll_ data0 6 io ah8 na etk_d15 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data1 3 io gpio_29 4 io mm2_txse0 5 io hsusb2_tll_ data1 6 io submit documentation feedback terminal description 31 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] ae16 - cam_d0 0 i l l 7 - yes 4 pu100/ lvds/ pd100 cmos - 2 ids gpio_99 4 i safe_mode 7 - ae15 - cam_d1 0 i l l 7 - yes 4 pu100/ lvds/ pd100 cmos - 2 ids gpio_100 4 i safe_mode 7 - ad17 - - 0 ids l l 7 - yes 4 pu100/ lvds/ pd100 cmos gpio_112 4 i safe_mode 7 - ae18 - - 0 ids l l 7 - yes 4 pu100/ lvds/ pd100 cmos gpio_114 4 i safe_mode 7 - ad16 - - 0 ids l l 7 - yes 4 pu100/ lvds/ pd100 cmos gpio_113 4 i safe_mode 7 - ae17 - - 0 ids l l 7 yes 4 pu100/ lvds/ pd100 cmos gpio_115 4 i safe_mode 7 - - g20 sdrc_a0 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - k20 sdrc_a1 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - j20 sdrc_a2 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - j21 sdrc_a3 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - u21 sdrc_a4 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - r20 sdrc_a5 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - m21 sdrc_a6 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - m20 sdrc_a7 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - n20 sdrc_a8 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - k21 sdrc_a9 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - y16 sdrc_a10 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - n21 sdrc_a11 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - r21 sdrc_a12 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - aa15 sdrc_a13 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - y12 sdrc_a14 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - aa18 sdrc_ba0 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - v20 sdrc_ba1 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - y15 sdrc_cke0 0 o h 1 7 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos safe_mode 7 - y13 sdrc_cke1 0 o h 1 7 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos safe_mode 7 (1) the drive strength is programmable vs the capacity load: load range = [2 pf to 6 pf] per default or [6 pf to 12 pf] according to the selected mode. terminal description 32 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] - a12 sdrc_clk 0 io l 0 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - d1 sdrc_d0 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - g1 sdrc_d1 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - g2 sdrc_d2 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - e1 sdrc_d3 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - d2 sdrc_d4 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - e2 sdrc_d5 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b3 sdrc_d6 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b4 sdrc_d7 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a10 sdrc_d8 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b11 sdrc_d9 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a11 sdrc_d10 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b12 sdrc_d11 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a16 sdrc_d12 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a17 sdrc_d13 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b17 sdrc_d14 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b18 sdrc_d15 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b7 sdrc_d16 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a5 sdrc_d17 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b6 sdrc_d18 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a6 sdrc_d19 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a8 sdrc_d20 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b9 sdrc_d21 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a9 sdrc_d22 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b10 sdrc_d23 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - c21 sdrc_d24 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - d20 sdrc_d25 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b19 sdrc_d26 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - c20 sdrc_d27 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - d21 sdrc_d28 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - e20 sdrc_d29 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - e21 sdrc_d30 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos submit documentation feedback terminal description 33 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] - g21 sdrc_d31 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - h1 sdrc_dm0 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - a14 sdrc_dm1 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - a4 sdrc_dm2 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - a18 sdrc_dm3 0 o 0 0 0 vdds_io no 4 (1) na lvds/ cmos - c2 sdrc_dqs0 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b15 sdrc_dqs1 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - b8 sdrc_dqs2 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - a19 sdrc_dqs3 0 io l z 0 vdds_io yes 4 (1) pu100/ lvds/ pd100 cmos - u20 sdrc_ncas 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos - b13 sdrc_nclk 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos - t21 sdrc_ncs0 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos - t20 sdrc_ncs1 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos - v21 sdrc_nras 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos - y18 sdrc_nwe 0 o 1 1 0 vdds_io no 4 (1) na lvds/ cmos ae21 - dss_data0 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods uart1_cts 2 i gpio_70 4 io safe_mode 7 - ae22 - dss_data1 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods uart1_rts 2 o gpio_71 4 io safe_mode 7 - ae23 - dss_data2 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_72 4 io safe_mode 7 - ae24 - dss_data3 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_73 4 io safe_mode 7 - ad23 - dss_data4 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods uart3_rx_irrx 2 i gpio_74 4 io safe_mode 7 - ad24 - dss_data5 0 io l l 7 - no 4 pu100/ lvds/ pd100 cmos - 1 ods uart3_tx_irtx 2 o gpio_75 4 io safe_mode 7 - terminal description 34 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] ac26 - dss_data10 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_80 4 io safe_mode 7 - ad26 - dss_data11 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_81 4 io safe_mode 7 - aa25 - dss_data12 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_82 4 io safe_mode 7 - y25 - dss_data13 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_83 4 io safe_mode 7 - aa26 - dss_data14 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_84 4 io safe_mode 7 - ab26 - dss_data15 0 io l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods gpio_85 4 io safe_mode 7 - f25 - dss_data20 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 - 1 o mcspi3_somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 - ac25 - dss_data22 0 o l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 - ab25 - dss_data23 0 o l l 7 - na 4 pu100/ lvds/ pd100 cmos - 1 ods dss_data5 3 io gpio_93 4 io safe_mode 7 - g25 - dss_pclk 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_66 4 io hw_dbg12 5 o safe_mode 7 - j2 - gpmc_a1 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_34 4 io safe_mode 7 - h1 - gpmc_a2 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_35 4 io safe_mode 7 - h2 - gpmc_a3 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_36 4 io submit documentation feedback terminal description 35 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] safe_mode 7 - g2 - gpmc_a4 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_37 4 io safe_mode 7 - f1 - gpmc_a5 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_38 4 io safe_mode 7 - f2 - gpmc_a6 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_39 4 io safe_mode 7 - e1 - gpmc_a7 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_40 4 io safe_mode 7 - e2 - gpmc_a8 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_41 4 io safe_mode 7 - d1 - gpmc_a9 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq2 1 i gpio_42 4 io safe_mode 7 - d2 - gpmc_a10 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq3 1 i gpio_43 4 io safe_mode 7 - n1 l1 gpmc_clk 0 o l 0 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_59 4 io safe_mode 7 - aa2 u2 gpmc_d0 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 aa1 u1 gpmc_d1 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ac2 v2 gpmc_d2 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ac1 v1 gpmc_d3 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ae5 aa3 gpmc_d4 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ad6 aa4 gpmc_d5 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ad5 y3 gpmc_d6 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ac5 y4 gpmc_d7 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 v1 r1 gpmc_d8 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_44 4 io safe_mode 7 - y1 t1 gpmc_d9 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_45 4 io safe_mode 7 - t1 n1 gpmc_d10 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_46 4 io safe_mode 7 - u2 p2 gpmc_d11 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_47 4 io safe_mode 7 - terminal description 36 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] u1 p1 gpmc_d12 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_48 4 io safe_mode 7 - p1 m1 gpmc_d13 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_49 4 io safe_mode 7 - l2 j2 gpmc_d14 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_50 4 io safe_mode 7 - m2 k2 gpmc_d15 0 io h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_51 4 io safe_mode 7 - ad10 aa9 gpmc_nadv_ale 0 o 0 0 0 vdds_io no 4 (1) na lvcmos k2 - gpmc_nbe0_cle 0 o l 0 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_60 4 io safe_mode 7 - j1 - gpmc_nbe1 0 o l l 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_61 4 io safe_mode 7 - ad8 aa8 gpmc_ncs0 0 o 1 1 0 vdds_io no 4 (1) na lvcmos ad1 w1 gpmc_ncs1 0 o h 1 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_52 4 io safe_mode 7 - a3 - gpmc_ncs2 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_53 4 io safe_mode 7 - b6 - gpmc_ncs3 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq0 1 i gpio_54 4 io safe_mode 7 - b4 - gpmc_ncs4 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq1 1 i mcbsp4_clkx 2 io gpt9_pwm_evt 3 io gpio_55 4 io safe_mode 7 - c4 - gpmc_ncs5 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq2 1 i mcbsp4_dr 2 i gpt10_pwm_evt 3 io gpio_56 4 io safe_mode 7 - b5 - gpmc_ncs6 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq3 1 i mcbsp4_dx 2 io gpt11_pwm_evt 3 io gpio_57 4 io safe_mode 7 - c5 - gpmc_ncs7 0 o h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt8_pwm_evt 3 io gpio_58 4 io submit documentation feedback terminal description 37 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] safe_mode 7 - n2 l2 gpmc_noe 0 o 1 1 0 vdds_io no 4 (1) na lvcmos m1 k1 gpmc_nwe 0 o 1 1 0 vdds_io no 4 (1) na lvcmos ac6 y5 gpmc_nwp 0 o l 0 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_62 4 io safe_mode 7 - ac11 y10 gpmc_wait0 0 i h h 0 vdds_io yes 4 (1) pu100/ lvcmos pd100 ac8 y8 gpmc_wait1 0 i h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_63 4 io safe_mode 7 - b3 - gpmc_wait2 0 i h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 gpio_64 4 io safe_mode 7 - c6 - gpmc_wait3 0 i h h 7 vdds_io yes 4 (1) pu100/ lvcmos pd100 sys_ndmareq1 1 i gpio_65 4 io safe_mode 7 - w19 - hsusb0_clk 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_120 4 io safe_mode 7 - v20 - hsusb0_data0 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart3_tx_irtx 2 o gpio_125 4 io safe_mode 7 - y20 - hsusb0_data1 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart3_rx_irrx 2 i gpio_130 4 io safe_mode 7 - v18 - hsusb0_data2 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart3_rts_sd 2 o gpio_131 4 io safe_mode 7 - w20 - hsusb0_data3 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart3_cts_rctx 2 io gpio_169 4 io safe_mode 7 - w17 - hsusb0_data4 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_188 4 io safe_mode 7 - y18 - hsusb0_data5 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_189 4 io safe_mode 7 - y19 - hsusb0_data6 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_190 4 io safe_mode 7 - y17 - hsusb0_data7 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_191 4 io safe_mode 7 - v19 - hsusb0_dir 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_122 4 io safe_mode 7 - (2) the capacity load range is [2 pf to 6 pf]. terminal description 38 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] w18 - hsusb0_nxt 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_124 4 io safe_mode 7 - u20 - hsusb0_stp 0 o h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_121 4 io safe_mode 7 - u15 - jtag_ntrst 0 i l l 0 vdds_io yes na pu100/ lvcmos pd100 w13 - jtag_rtck 0 o l 0 0 vdds_io yes 4 pu100/ lvcmos pd100 v14 - jtag_tck 0 i l l 0 vdds_io yes na pu100/ lvcmos pd100 u16 - jtag_tdi 0 i h h 0 vdds_io yes na pu100/ lvcmos pd100 y13 - jtag_tdo 0 o l z 0 vdds_io yes 4 pu100/ lvcmos pd100 v15 - jtag_tms_tmsc 0 io h h 0 vdds_io yes 4 pu100/ lvcmos pd100 n19 - mmc1_clk 0 o l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 o gpio_120 4 io safe_mode 7 - l18 - mmc1_cmd 0 io l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 o gpio_121 4 io safe_mode 7 - m19 - mmc1_dat0 0 io l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 io gpio_122 4 io safe_mode 7 - m18 - mmc1_dat1 0 io l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 io gpio_123 4 io safe_mode 7 - k18 - mmc1_dat2 0 io l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 io gpio_124 4 io safe_mode 7 - n20 - mmc1_dat3 0 io l l 7 vdds_mmc1 yes 8 pu100/ lvcmos pd100 - 1 io gpio_125 4 io safe_mode 7 - m20 - mmc1_dat4 0 io l l 7 vdds_mmc1a no 8 pu/pd (3) lvcmos - 2 io gpio_126 4 io safe_mode 7 - p17 - mmc1_dat5 0 io l l 7 vdds_mmc1a no 8 pu/pd (3) lvcmos - 2 o gpio_127 4 io safe_mode 7 - p18 - mmc1_dat6 0 io l l 7 vdds_mmc1a no 8 pu/pd (3) lvcmos - 2 o gpio_128 4 io safe_mode 7 - (3) the pu nominal drive strength of this io cell is equal to 25 m a @ 1.8 v and 41.6 m a @ 3.0 v. the pd nominal drive strength of this io cell is equal to 1 ma @ 1.8 v and 1.66 ma @ 3.0 v. submit documentation feedback terminal description 39 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] p19 - mmc1_dat7 0 io l l 7 vdds_mmc1a no 8 pu/pd (3) lvcmos - 2 o gpio_129 4 io safe_mode 7 - j25 - i2c1_scl 0 iod h h 0 vdds_io yes 3 pu100/ open drain pd100 j24 - i2c1_sda 0 iod h h 0 vdds_io yes 3 pu100/ open drain pd100 c2 - i2c2_scl 0 iod h h 7 vdds_io yes 3 pu100/ lvcmos pd100 open drain gpio_168 4 io 4 safe_mode 7 - 4 c1 - i2c2_sda 0 iod h h 7 vdds_io yes 3 pu100/ lvcmos pd100 open drain gpio_183 4 io 4 safe_mode 7 - 4 ab4 - i2c3_scl 0 iod h h 7 vdds_io yes 3 pu100/ lvcmos pd100 open drain gpio_184 4 io 4 safe_mode 7 - 4 ac4 - i2c3_sda 0 iod h h 7 vdds_io yes 3 pu100/ lvcmos pd100 open drain gpio_185 4 io 4 safe_mode 7 - 4 u19 - mcbsp1_clkr 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi4_clk 1 io - 2 i gpio_156 4 io safe_mode 7 - t17 - mcbsp1_clkx 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp3_clkx 2 io gpio_162 4 io safe_mode 7 - t20 - mcbsp1_dr 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi4_somi 1 io mcbsp3_dr 2 i gpio_159 4 io safe_mode 7 - u17 - mcbsp1_dx 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi4_simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 - v17 - mcbsp1_fsr 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i cam_global_reset 2 io gpio_157 4 io safe_mode 7 - p20 - mcbsp1_fsx 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io safe_mode 7 - r18 - mcbsp2_clkx 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 gpio_117 4 io safe_mode 7 - (4) the buffer strength of this io cell is programmable (2, 4, 6, or 8 ma) according to the selected mode; the default value is described in the above table. terminal description 40 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] t18 - mcbsp2_dr 0 i l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 gpio_118 4 io safe_mode 7 - r19 - mcbsp2_dx 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 gpio_119 4 io safe_mode 7 - u18 - mcbsp2_fsx 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 gpio_116 4 io safe_mode 7 - p9 - mcspi1_clk 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 mmc2_dat4 1 io gpio_171 4 io safe_mode 7 - r7 - mcspi1_cs0 0 io h h 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 mmc2_dat7 1 io gpio_174 4 io safe_mode 7 - r9 - mcspi1_cs2 0 o h h 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 mmc3_clk 3 o gpio_176 4 io safe_mode 7 - p8 - mcspi1_simo 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 mmc2_dat5 1 io gpio_172 4 io safe_mode 7 - p7 - mcspi1_somi 0 io l l 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 mmc2_dat6 1 io gpio_173 4 io safe_mode 7 - w7 - mcspi2_clk 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_tll_data7 2 io hsusb2_data7 3 o gpio_178 4 io safe_mode 7 - v8 - mcspi2_cs0 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpt11_pwm_evt 1 io hsusb2_tll_data6 2 io hsusb2_data6 3 o gpio_181 4 io safe_mode 7 - w8 - mcspi2_simo 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpt9_pwm_evt 1 io hsusb2_tll_data4 2 io hsusb2_data4 3 i gpio_179 4 io safe_mode 7 - u8 - mcspi2_somi 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpt10_pwm_evt 1 io hsusb2_tll_data5 2 io hsusb2_data5 3 o gpio_180 4 io safe_mode 7 - submit documentation feedback terminal description 41 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] w10 - mmc2_clk 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_clk 1 io gpio_130 4 io safe_mode 7 - r10 - mmc2_cmd 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_simo 1 io gpio_131 4 io safe_mode 7 - t10 - mmc2_dat0 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_somi 1 io gpio_132 4 io safe_mode 7 - t9 - mmc2_dat1 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_133 4 io safe_mode 7 - u10 - mmc2_dat2 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 - u9 - mmc2_dat3 0 io h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 - v10 - mmc2_dat4 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 - r2 - uart1_rts 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_149 4 io safe_mode 7 - h3 - uart1_rx 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp1_clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 - l4 - uart1_tx 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_148 4 io safe_mode 7 - y24 - uart2_cts 0 i h h 7 vdds_io yes 4 pu100/ lvcmos pd100 mcbsp3_dx 1 io gpt9_pwm_evt 2 io gpio_144 4 io safe_mode 7 - aa24 - uart2_rts 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 mcbsp3_dr 1 i gpt10_pwm_evt 2 io gpio_145 4 io safe_mode 7 - ad21 - uart2_rx 0 i h h 7 vdds_io yes 4 pu100/ lvcmos pd100 mcbsp3_fsx 1 io terminal description 42 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] gpt8_pwm_evt 2 io gpio_147 4 io safe_mode 7 - ad22 - uart2_tx 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 mcbsp3_clkx 1 io gpt11_pwm_evt 2 io gpio_146 4 io safe_mode 7 - f23 - uart3_cts_rctx 0 io h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_163 4 io safe_mode 7 - f24 - uart3_rts_sd 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_164 4 io safe_mode 7 - h24 - uart3_rx_irrx 0 i h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_165 4 io safe_mode 7 - g24 - uart3_tx_irtx 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_166 4 io safe_mode 7 - j23 - hdq_sio 0 iod h h 7 vdds_io yes 4 pu100/ lvcmos pd100 open drain sys_altclk 1 i i2c2_sccbe 2 o i2c3_sccbe 3 o gpio_170 4 io safe_mode 7 - ad15 - i2c4_scl 0 iod h h 0 vdds_io yes 3 pu100/ lvcmos pd100 open drain sys_nvmode1 1 o 4 safe_mode 7 - 4 w16 - i2c4_sda 0 iod h h 0 vdds_io yes 3 pu100/ lvcmos pd100 open drain sys_nvmode2 1 o 4 safe_mode 7 - 4 k4 - sad2d_clk26mi 0 o l 0 (pd) 0 vdds_io yes 4 pu100/ lvcmos pd100 f3 - sys_boot0 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_2 4 io safe_mode 7 - d3 - sys_boot1 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_3 4 io safe_mode 7 - c3 - sys_boot2 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_4 4 io safe_mode 7 - e3 - sys_boot3 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_5 4 io safe_mode 7 - e4 - sys_boot4 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 mmc2_dir_dat2 1 o gpio_6 4 io safe_mode 7 - g3 - sys_boot5 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 mmc2_dir_dat3 1 o gpio_7 4 io submit documentation feedback terminal description 43 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] safe_mode 7 - d4 - sys_boot6 0 i z z 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_8 4 io safe_mode 7 - ae14 - sys_clkout1 0 o l l 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_10 4 io safe_mode 7 - w11 - sys_clkout2 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_186 4 io safe_mode 7 - w15 - sys_clkreq 0 io 0 1 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_1 4 io safe_mode 7 - v16 - sys_nirq 0 i h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_0 4 io safe_mode 7 - v13 - sys_nrespwron 0 i z i na vdds_io yes na na lvcmos ad7 aa5 sys_nreswarm 0 iod 0 1 (pu) 0 vdds_io yes 4 pu100/ lvcmos pd100 open drain gpio_30 4 io safe_mode 7 - v12 - sys_off_mode 0 o 0 l 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_9 4 io safe_mode 7 - af19 - sys_xtalin 0 i z i na vdds_io yes na na lvcmos af20 - sys_xtalout 0 o z o na vdds_io yes na na lvcmos b1 - sys_ipmcsws 0 ai z na na vdds_io no na na analog a2 - sys_opmcsws 0 ao 0 na na vdds_io no na na analog w26 - tv_out1 0 ao z 0 0 vdda_dac no 8 na 10-bit dac v26 - tv_out2 0 ao z 0 0 vdda_dac no 8 na 10-bit dac w25 - tv_vfb1 0 o z na 0 vdda_dac no 2 na 10-bit dac u24 - tv_vfb2 0 o z na 0 vdda_dac no 2 na 10-bit dac v23 - tv_vref 0 i z na 0 vdda_dac no na na 10-bit dac ae20 - sys_32k 0 i z i na vdds_io yes na na lvcmos a24 - cam_d2 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_101 4 io hw_dbg4 5 o safe_mode 7 - b24 - cam_d3 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_102 4 io hw_dbg5 5 o safe_mode 7 - d24 - cam_d4 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_103 4 io hw_dbg6 5 o safe_mode 7 - c24 - cam_d5 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_104 4 io hw_dbg7 5 o safe_mode 7 - terminal description 44 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] d25 - cam_d10 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_109 4 io hw_dbg8 5 o safe_mode 7 - e26 - cam_d11 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_110 4 io hw_dbg9 5 o safe_mode 7 - b23 - cam_fld 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 cam_global_reset 2 io gpio_98 4 io hw_dbg3 5 o safe_mode 7 - c23 - cam_hs 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_94 4 io hw_dbg0 5 o safe_mode 7 - c26 - cam_pclk 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_97 4 io hw_dbg2 5 o safe_mode 7 - d26 - cam_strobe 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_126 4 io hw_dbg11 5 o safe_mode 7 - c25 - cam_xclka 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_96 4 io safe_mode 7 - e25 - cam_xclkb 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpio_111 4 io safe_mode 7 - p25 - cam_d6 0 i l l 7 vdds_csib na 4 pu100/ sublvds pd100 gpio_105 4 io safe_mode 7 - p26 - cam_d7 0 i l l 7 vdds_csib na 4 pu100/ sublvds pd100 gpio_106 4 io safe_mode 7 - n25 - cam_d8 0 i l l 7 vdds_csib na 4 pu100/ sublvds pd100 gpio_107 4 io safe_mode 7 - n26 - cam_d9 0 i l l 7 vdds_csib na 4 pu100/ sublvds pd100 gpio_108 4 io safe_mode 7 - d23 - cam_vs 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_95 4 io hw_dbg1 5 o safe_mode 7 - submit documentation feedback terminal description 45 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] a23 - cam_wen 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 cam_shutter 2 o gpio_167 4 io hw_dbg10 5 o safe_mode 7 - f26 - dss_acbias 0 o l l 7 vdds_io yes 8 pu100/ lvcmos pd100 gpio_69 4 io safe_mode 7 - g26 - dss_data6 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 uart1_tx 2 o gpio_76 4 io hw_dbg14 5 o safe_mode 7 - h25 - dss_data7 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 uart1_rx 2 i gpio_77 4 io hw_dbg15 5 o safe_mode 7 - h26 - dss_data8 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 gpio_78 4 io hw_dbg16 5 o safe_mode 7 - j26 - dss_data9 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 gpio_79 4 io hw_dbg17 5 o safe_mode 7 - l25 - dss_data16 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 gpio_86 4 io safe_mode 7 - l26 - dss_data17 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 gpio_87 4 io safe_mode 7 - m24 - dss_data18 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 - 1 o mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 - m26 - dss_data19 0 io l l 7 vdds_io yes 8 pu100/ lvcmos pd100 - 1 o mcspi3_simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 - n24 - dss_data21 0 o l l 7 vdds_io yes 8 pu100/ lvcmos pd100 - 1 o mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 - terminal description 46 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] k24 - dss_hsync 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_67 4 io hw_dbg13 5 o safe_mode 7 - m25 - dss_vsync 0 o h h 7 vdds_io yes 4 pu100/ lvcmos pd100 gpio_68 4 io safe_mode 7 - r8 - mcspi1_cs1 0 o h h 7 vdds_io yes 4 (4) pu100/ lvcmos pd100 - 1 i mmc3_cmd 3 io gpio_175 4 io safe_mode 7 - t8 - mcspi1_cs3 0 o h h 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_tll_data2 2 io hsusb2_data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 - v9 - mcspi2_cs1 0 o l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 gpt8_pwm_evt 1 io hsusb2_tll_data3 2 io hsusb2_data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 - t19 - mcbsp_clks 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 cam_shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 - ab2 - etk_clk 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp5_clkx 1 io mmc3_clk 2 o hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hsusb1_tll_stp 6 i hw_dbg0 7 o ab3 - etk_ctl 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io hsusb1_tll_clk 6 o hw_dbg1 7 o ac3 - etk_d0 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_simo 1 io mmc3_dat4 2 io hsusb1_data0 3 io gpio_14 4 io mm1_rxrcv 5 io hsusb1_tll_data0 6 io hw_dbg2 7 o submit documentation feedback terminal description 47 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] ad4 - etk_d1 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_somi 1 io hsusb1_data1 3 io gpio_15 4 io mm1_txse0 5 io hsusb1_tll_data1 6 io hw_dbg3 7 o ad3 - etk_d2 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_cs0 1 io hsusb1_data2 3 io gpio_16 4 io mm1_txdat 5 io hsusb1_tll_data2 6 io hw_dbg4 7 o aa3 - etk_d3 0 o h h 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_clk 1 io mmc3_dat3 2 io hsusb1_data7 3 io gpio_17 4 io hsusb1_tll_data7 6 io hw_dbg5 7 o y3 - etk_d4 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_data4 3 io gpio_18 4 io hsusb1_tll_data4 6 io hw_dbg6 7 o ab1 - etk_d5 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_data5 3 io gpio_19 4 io hsusb1_tll_data5 6 io hw_dbg7 7 o ae3 - etk_d6 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcbsp5_dx 1 io mmc3_dat2 2 io hsusb1_data6 3 io gpio_20 4 io hsusb1_tll_data6 6 io hw_dbg8 7 o ad2 - etk_d7 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 mcspi3_cs1 1 o mmc3_dat7 2 io hsusb1_data3 3 io gpio_21 4 io mm1_txen_n 5 io hsusb1_tll_data3 6 io hw_dbg9 7 o aa4 - etk_d8 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 sys_drm_msecure 1 o mmc3_dat6 2 io terminal description 48 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] hsusb1_dir 3 i gpio_22 4 io hsusb1_tll_dir 6 o hw_dbg10 7 o v2 - etk_d9 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 sys_secure_indicator 1 o mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hsusb1_tll_nxt 6 o hw_dbg11 7 o ae4 - etk_d10 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hsusb2_tll_clk 6 o hw_dbg12 7 o af6 - etk_d11 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hsusb2_tll_stp 6 i hw_dbg13 7 o ae6 - etk_d12 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_dir 3 i gpio_26 4 io hsusb2_tll_dir 6 o hw_dbg14 7 o af7 - etk_d13 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_nxt 3 i gpio_27 4 io mm2_rxdm 5 io hsusb2_tll_nxt 6 o hw_dbg15 7 o af9 - etk_d14 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_data0 3 io gpio_28 4 io mm2_rxrcv 5 io hsusb2_tll_data0 6 io hw_dbg16 7 o ae9 - etk_d15 0 o l l 4 vdds_io yes 4 (2) pu100/ lvcmos pd100 hsusb2_data1 3 io gpio_29 4 io mm2_txse0 5 io hsusb2_tll_data1 6 io hw_dbg17 7 o y15 - jtag_emu0 0 io h h 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_11 4 io safe_mode 7 - y14 - jtag_emu1 0 io h h 0 vdds_io yes 4 pu100/ lvcmos pd100 gpio_31 4 io safe_mode 7 - submit documentation feedback terminal description 49 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] u3 - mcbsp3_clkx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart2_tx 1 o gpio_142 4 io hsusb3_tll_data6 5 io safe_mode 7 - n3 - mcbsp3_dr (5) 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart2_rts 1 o gpio_141 4 io hsusb3_tll_data5 5 io safe_mode 7 - p3 - mcbsp3_dx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart2_cts 1 i gpio_140 4 io hsusb3_tll_data4 5 io safe_mode 7 - w3 - mcbsp3_fsx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 uart2_rx 1 i gpio_143 4 io hsusb3_tll_data7 5 io safe_mode 7 - v3 - mcbsp4_clkx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_152 4 io hsusb3_tll_data1 5 io mm3_txse0 6 io safe_mode 7 - u4 - mcbsp4_dr (5) 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_153 4 io hsusb3_tll_data0 5 io mm3_rxrcv 6 io safe_mode 7 - r3 - mcbsp4_dx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_154 4 io hsusb3_tll_data2 5 io mm3_txdat 6 io safe_mode 7 - t3 - mcbsp4_fsx (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 o gpio_155 4 io hsusb3_tll_data3 5 io mm3_txen_n 6 io safe_mode 7 - m3 - mmc2_dat5 (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io gpio_137 4 io hsusb3_tll_stp 5 i mm3_rxdp 6 io safe_mode 7 - (5) this functionality is not supported. terminal description 50 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-2. ball characteristics (cbc pkg.) (continued) ball ball pin mode type ball ball reset power hys buffer pullup io bottom top name [5] [6] reset reset rel. [10] [11] streng /down cell [1] [2] [4] state rel. mode th type [14] [7] state [9] (ma) [13] [8] [12] l3 - mmc2_dat6 (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mmc2_dir_cmd 1 o cam_shutter 2 o mmc3_dat2 3 io gpio_138 4 io hsusb3_tll_dir 5 o safe_mode 7 - k3 - mmc2_dat7 (5) 0 io l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 mmc2_clkin 1 i mmc3_dat3 3 io gpio_139 4 io hsusb3_tll_nxt 5 io mm3_rxdm 6 io safe_mode 7 - w2 - uart1_cts (5) 0 i l l 7 vdds_io yes 4 (2) pu100/ lvcmos pd100 - 1 i gpio_150 4 io hsusb3_tll_clk 5 o safe_mode 7 - submit documentation feedback terminal description 51 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (1) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] d7 sdrc_d0 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c5 sdrc_d1 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c6 sdrc_d2 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b5 sdrc_d3 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d9 sdrc_d4 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d10 sdrc_d5 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c7 sdrc_d6 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b7 sdrc_d7 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b11 sdrc_d8 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c12 sdrc_d9 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b12 sdrc_d10 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d13 sdrc_d11 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c13 sdrc_d12 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b14 sdrc_d13 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a14 sdrc_d14 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b15 sdrc_d15 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c9 sdrc_d16 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos e12 sdrc_d17 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b8 sdrc_d18 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b9 sdrc_d19 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c10 sdrc_d20 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b10 sdrc_d21 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d12 sdrc_d22 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos e13 sdrc_d23 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos e15 sdrc_d24 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d15 sdrc_d25 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c15 sdrc_d26 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b16 sdrc_d27 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c16 sdrc_d28 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos d16 sdrc_d29 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b17 sdrc_d30 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos b18 sdrc_d31 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos c18 sdrc_ba0 0 o 0 0 0 vdds_ mem no 4 na lvcmos d18 sdrc_ba1 0 o 0 0 0 vdds_ mem no 4 na lvcmos a4 sdrc_a0 0 o 0 0 0 vdds_ mem no 4 na lvcmos b4 sdrc_a1 0 o 0 0 0 vdds_ mem no 4 na lvcmos d6 sdrc_a2 0 o 0 0 0 vdds_ mem no 4 na lvcmos b3 sdrc_a3 0 o 0 0 0 vdds_ mem no 4 na lvcmos b2 sdrc_a4 0 o 0 0 0 vdds_ mem no 4 na lvcmos c3 sdrc_a5 0 o 0 0 0 vdds_ mem no 4 na lvcmos e3 sdrc_a6 0 o 0 0 0 vdds_ mem no 4 na lvcmos f6 sdrc_a7 0 o 0 0 0 vdds_ mem no 4 na lvcmos e10 sdrc_a8 0 o 0 0 0 vdds_ mem no 4 na lvcmos e9 sdrc_a9 0 o 0 0 0 vdds_ mem no 4 na lvcmos e7 sdrc_a10 0 o 0 0 0 vdds_ mem no 4 na lvcmos g6 sdrc_a11 0 o 0 0 0 vdds_ mem no 4 na lvcmos g7 sdrc_a12 0 o 0 0 0 vdds_ mem no 4 na lvcmos f7 sdrc_a13 0 o 0 0 0 vdds_ mem no 4 na lvcmos f9 sdrc_a14 0 o 0 0 0 vdds_ mem no 4 na lvcmos a19 sdrc_ncs0 0 o 1 1 0 vdds_ mem no 4 na lvcmos b19 sdrc_ncs1 0 o 1 1 0 vdds_ mem no 4 na lvcmos a10 sdrc_clk 0 io l 0 0 vdds_ mem yes 4 pu/ pd lvcmos a11 sdrc_nclk 0 o 1 1 0 vdds_ mem no 4 na lvcmos (1) na in this table stands for not applicable. terminal description 52 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] b20 sdrc_cke0 0 o h 1 7 vdds_ mem yes 4 pu/ pd lvcmos safe_mode 7 c20 sdrc_cke1 0 o h 1 7 vdds_ mem yes 4 pu/ pd lvcmos safe_mode 7 d19 sdrc_nras 0 o 1 1 0 vdds_ mem no 4 na lvcmos c19 sdrc_ncas 0 o 1 1 0 vdds_ mem no 4 na lvcmos a20 sdrc_nwe 0 o 1 1 0 vdds_ mem no 4 na lvcmos b6 sdrc_dm0 0 o 0 0 0 vdds_ mem no 4 na lvcmos b13 sdrc_dm1 0 o 0 0 0 vdds_ mem no 4 na lvcmos a7 sdrc_dm2 0 o 0 0 0 vdds_ mem no 4 na lvcmos a16 sdrc_dm3 0 o 0 0 0 vdds_ mem no 4 na lvcmos a5 sdrc_dqs0 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a13 sdrc_dqs1 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a8 sdrc_dqs2 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos a17 sdrc_dqs3 0 io l z 0 vdds_ mem yes 4 pu/ pd lvcmos k4 gpmc_a1 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_34 4 io safe_mode 7 k3 gpmc_a2 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_35 4 io safe_mode 7 k2 gpmc_a3 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_36 4 io safe_mode 7 j4 gpmc_a4 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_37 4 io safe_mode 7 j3 gpmc_a5 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_38 4 io safe_mode 7 j2 gpmc_a6 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_39 4 io safe_mode 7 j1 gpmc_a7 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_40 4 io safe_mode 7 h1 gpmc_a8 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_41 4 io safe_mode 7 h2 gpmc_a9 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq2 1 i gpio_42 4 io safe_mode 7 g2 gpmc_a10 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq3 1 i gpio_43 4 io safe_mode 7 l2 gpmc_d0 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos m1 gpmc_d1 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos m2 gpmc_d2 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos n2 gpmc_d3 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos m3 gpmc_d4 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos p1 gpmc_d5 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos p2 gpmc_d6 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos submit documentation feedback terminal description 53 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] r1 gpmc_d7 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos r2 gpmc_d8 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_44 4 io safe_mode 7 t2 gpmc_d9 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_45 4 io safe_mode 7 u1 gpmc_d10 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_46 4 io safe_mode 7 r3 gpmc_d11 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_47 4 io safe_mode 7 t3 gpmc_d12 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_48 4 io safe_mode 7 u2 gpmc_d13 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_49 4 io safe_mode 7 v1 gpmc_d14 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_50 4 io safe_mode 7 v2 gpmc_d15 0 io h h 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_51 4 io safe_mode 7 e2 gpmc_ncs0 0 o 1 1 0 vdds_ mem no 4 na lvcmos d2 gpmc_ncs3 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq0 1 i gpio_54 4 io safe_mode 7 f4 gpmc_ncs4 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq1 1 i mcbsp4_ clkx 2 io gpt9_pwm_evt 3 io gpio_55 4 io safe_mode 7 g5 gpmc_ncs5 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq2 1 i mcbsp4_dr 2 i gpt10_pwm_evt 3 io gpio_56 4 io safe_mode 7 f3 gpmc_ncs6 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq3 1 i mcbsp4_dx 2 io gpt11_pwm_evt 3 io gpio_57 4 io safe_mode 7 g4 gpmc_ncs7 0 o h h 7 vdds_ mem yes 4 pu/ pd lvcmos gpmc_io_dir 1 o mcbsp4_fsx 2 io gpt8_pwm_evt 3 io gpio_58 4 io safe_mode 7 terminal description 54 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] w2 gpmc_clk 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_59 4 io safe_mode 7 f1 gpmc_nadv_ale 0 o 0 0 0 vdds_ mem no 4 na lvcmos f2 gpmc_noe 0 o 1 1 0 vdds_ mem no 4 na lvcmos g3 gpmc_nwe 0 o 1 1 0 vdds_ mem no 4 na lvcmos k5 gpmc_nbe0_cle 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_60 4 io safe_mode 7 l1 gpmc_nbe1 0 o l l 7 vdds_ mem yes 4 pu/ pd lvcmos gpio_61 4 io safe_mode 7 e1 gpmc_nwp 0 o l 0 0 vdds_ mem yes 4 pu/ pd lvcmos gpio_62 4 io safe_mode 7 c1 gpmc_wait0 0 i h h 0 vdds_ mem yes na pu/ pd lvcmos c2 gpmc_wait3 0 i h h 7 vdds_ mem yes 4 pu/ pd lvcmos sys_ ndmareq1 1 i gpio_65 4 io safe_mode 7 g22 dss_pclk 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_66 4 io safe_mode 7 e22 dss_hsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_67 4 io safe_mode 7 f22 dss_vsync 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_68 4 io safe_mode 7 j21 dss_acbias 0 o l l 7 vdds yes 8 pu/ pd lvcmos gpio_69 4 io safe_mode 7 ac19 dss_data0 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart1_cts 2 i gpio_70 4 io safe_mode 7 ab19 dss_data1 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart1_rts 2 o gpio_71 4 io safe_mode 7 ad20 dss_data2 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos gpio_72 4 io safe_mode 7 ac20 dss_data3 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos gpio_73 4 io safe_mode 7 ad21 dss_data4 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart3_rx_ irrx 2 i gpio_74 4 io safe_mode 7 ac21 dss_data5 0 io l l 7 vdds no 4 pu/ pd lvds/ cmos uart3_tx_ irtx 2 o gpio_75 4 io safe_mode 7 submit documentation feedback terminal description 55 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] d24 dss_data6 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_tx 2 o gpio_76 4 io safe_mode 7 e23 dss_data7 0 io l l 7 vdds yes 8 pu/ pd lvcmos uart1_rx 2 i gpio_77 4 io safe_mode 7 e24 dss_data8 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_78 4 io safe_mode 7 f23 dss_data9 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_79 4 io safe_mode 7 ac22 dss_data10 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_80 4 io safe_mode 7 ac23 dss_data11 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_81 4 io safe_mode 7 ab22 dss_data12 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_82 4 io safe_mode 7 y22 dss_data13 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_83 4 io safe_mode 7 w22 dss_data14 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_84 4 io safe_mode 7 v22 dss_data15 0 io l l 7 vdds na 4 pu/ pd lvds/ cmos gpio_85 4 io safe_mode 7 j22 dss_data16 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_86 4 io safe_mode 7 g23 dss_data17 0 io l l 7 vdds yes 8 pu/ pd lvcmos gpio_87 4 io safe_mode 7 g24 dss_data18 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_clk 2 io dss_data0 3 io gpio_88 4 io safe_mode 7 h23 dss_data19 0 io l l 7 vdds yes 8 pu/ pd lvcmos mcspi3_ simo 2 io dss_data1 3 io gpio_89 4 io safe_mode 7 d23 dss_data20 0 o h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 2 io dss_data2 3 io gpio_90 4 io safe_mode 7 k22 dss_data21 0 o l l 7 vdds yes 8 pu/ pd lvcmos terminal description 56 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] mcspi3_cs0 2 io dss_data3 3 io gpio_91 4 io safe_mode 7 v21 dss_data22 0 o l l 7 vdds na 4 pu/ pd lvds/ cmos mcspi3_cs1 2 o dss_data4 3 io gpio_92 4 io safe_mode 7 w21 dss_data23 0 o l l 7 vdds na 4 pu/ pd lvds/ cmos dss_data5 3 io gpio_93 4 io safe_mode 7 aa23 tv_out2 0 o z 0 0 vddadac 8 na 10-bit dac ab24 tv_out1 0 o z 0 0 vddadac 8 na 10-bit dac ab23 tv_vfb1 0 o z na 0 vddadac na 10-bit dac y23 tv_vfb2 0 o z na 0 vddadac na 10-bit dac y24 tv_vref 0 i z na 0 vddadac na 10-bit dac a22 cam_hs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_94 4 io safe_mode 7 e18 cam_vs 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_95 4 io safe_mode 7 b22 cam_ xclka 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_96 4 io safe_mode 7 j19 cam_pclk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_97 4 io safe_mode 7 h24 cam_fld 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_98 4 io safe_mode 7 ab18 cam_d0 0 i l l 7 vdds yes 4 pd lvds/ cmos gpio_99 4 i safe_mode 7 ac18 cam_d1 0 i l l 7 vdds yes 4 pd lvds/ cmos gpio_100 4 i safe_mode 7 g19 cam_d2 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_101 4 io safe_mode 7 f19 cam_d3 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_102 4 io safe_mode 7 g20 cam_d4 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_103 4 io safe_mode 7 b21 cam_d5 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_104 4 io safe_mode 7 l24 cam_d6 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_105 4 io submit documentation feedback terminal description 57 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] safe_mode 7 k24 cam_d7 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_106 4 io safe_mode 7 j23 cam_d8 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_107 4 io safe_mode 7 k23 cam_d9 0 i l l 7 vdds na 4 pd lvds/ cmos gpio_108 4 io safe_mode 7 f21 cam_d10 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_109 4 io safe_mode 7 g21 cam_d11 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_110 4 io safe_mode 7 c22 cam_ xclkb 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_111 4 io safe_mode 7 f18 cam_wen 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_167 4 io safe_mode 7 j20 cam_ strobe 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_126 4 io safe_mode 7 v20 mcbsp2_fsx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_116 4 io safe_mode 7 t21 mcbsp2_ clkx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_117 4 io safe_mode 7 v19 mcbsp2_dr 0 i pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_118 4 io safe_mode 7 r20 mcbsp2_dx 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos gpio_119 4 io safe_mode 7 m23 mmc1_clk 0 o l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_120 4 io safe_mode 7 l23 mmc1_cmd 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_121 4 io safe_mode 7 m22 mmc1_dat0 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_122 4 io safe_mode 7 m21 mmc1_dat1 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_123 4 io safe_mode 7 m20 mmc1_dat2 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_124 4 io (2) the buffer strength of this io cell is programmable (2, 4, 6, or 8 ma) according to the selected mode; the default value is described in the above table. terminal description 58 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] safe_mode 7 n23 mmc1_dat3 0 io l l 7 mmc1_ vdds yes 8 pu/ pd lvcmos gpio_125 4 io safe_mode 7 n22 mmc1_dat4 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_126 4 io safe_mode 7 n21 mmc1_dat5 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_127 4 io safe_mode 7 n20 mmc1_dat6 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_128 4 io safe_mode 7 p24 mmc1_dat7 0 io l l 7 vdds_ mmc1a no 8 pd lvcmos gpio_129 4 io safe_mode 7 y1 mmc2_clk 0 o l l 7 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io gpio_130 4 io safe_mode 7 ab5 mmc2_ cmd 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io gpio_131 4 io safe_mode 7 ab3 mmc2_ dat0 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io gpio_132 4 io safe_mode 7 y3 mmc2_ dat1 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_133 4 io safe_mode 7 w3 mmc2_ dat2 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o gpio_134 4 io safe_mode 7 v3 mmc2_ dat3 0 io h h 7 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io gpio_135 4 io safe_mode 7 ab2 mmc2_ dat4 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat0 1 o mmc3_dat0 3 io gpio_136 4 io safe_mode 7 aa2 mmc2_ dat5 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat1 1 o cam_global_reset 2 io mmc3_dat1 3 io gpio_137 4 io safe_mode 7 y2 mmc2_ dat6 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_dir_ cmd 1 o cam_ shutter 2 o mmc3_dat2 3 io submit documentation feedback terminal description 59 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] gpio_138 4 io safe_mode 7 aa1 mmc2_ dat7 0 io l l 7 vdds yes 4 pu/ pd lvcmos mmc2_ clkin 1 i mmc3_dat3 3 io gpio_139 4 io safe_mode 7 v6 mcbsp3_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_cts 1 i gpio_140 4 io safe_mode 7 v5 mcbsp3_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos uart2_rts 1 o gpio_141 4 io safe_mode 7 w4 mcbsp3_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_tx 1 o gpio_142 4 io safe_mode 7 v4 mcbsp3_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart2_rx 1 i gpio_143 4 io safe_mode 7 w7 uart1_tx 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_148 4 io safe_mode 7 w6 uart1_rts 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_149 4 io safe_mode 7 ac2 uart1_cts 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_150 4 io safe_mode 7 v7 uart1_rx 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcbsp1_ clkr 2 io mcspi4_clk 3 io gpio_151 4 io safe_mode 7 w19 mcbsp1_ clkr 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_clk 1 io gpio_156 4 io safe_mode 7 ab20 mcbsp1_fsr 0 io l l 7 vdds yes 4 pu/ pd lvcmos cam_global_reset 2 io gpio_157 4 io safe_mode 7 w18 mcbsp1_dx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ simo 1 io mcbsp3_dx 2 io gpio_158 4 io safe_mode 7 y18 mcbsp1_dr 0 i l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_ somi 1 io mcbsp3_dr 2 o gpio_159 4 io terminal description 60 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] safe_mode 7 aa18 mcbsp_clks 0 i l l 7 vdds yes 4 pu/ pd lvcmos cam_ shutter 2 o gpio_160 4 io uart1_cts 5 i safe_mode 7 aa19 mcbsp1_fsx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcspi4_cs0 1 io mcbsp3_fsx 2 io gpio_161 4 io safe_mode 7 v18 mcbsp1_ clkx 0 io l l 7 vdds yes 4 pu/ pd lvcmos mcbsp3_ clkx 2 io gpio_162 4 io safe_mode 7 a23 uart3_cts_ rctx 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpio_163 4 io safe_mode 7 b23 uart3_rts_ sd 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_164 4 io safe_mode 7 b24 uart3_rx_ irrx 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_165 4 io safe_mode 7 c23 uart3_tx_ irtx 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_166 4 io safe_mode 7 r21 hsusb0_clk 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_120 4 io safe_mode 7 r23 hsusb0_stp 0 o h h 7 vdds yes 4 pu/ pd lvcmos gpio_121 4 io safe_mode 7 p23 hsusb0_dir 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_122 4 io safe_mode 7 r22 hsusb0_nxt 0 i l l 7 vdds yes 4 pu/ pd lvcmos gpio_124 4 io safe_mode 7 t24 hsusb0_ data0 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_tx_ irtx 2 o gpio_125 4 io safe_mode 7 t23 hsusb0_ data1 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rx_ irrx 2 i gpio_130 4 io safe_mode 7 u24 hsusb0_ data2 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_rts_ sd 2 o gpio_131 4 io safe_mode 7 u23 hsusb0_ data3 0 io l l 7 vdds yes 4 pu/ pd lvcmos uart3_cts_ rctx 2 io gpio_169 4 io submit documentation feedback terminal description 61 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] safe_mode 7 w24 hsusb0_ data4 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_188 4 io safe_mode 7 v23 hsusb0_ data5 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_189 4 io safe_mode 7 w23 hsusb0_ data6 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_190 4 io safe_mode 7 t22 hsusb0_ data7 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpio_191 4 io safe_mode 7 k20 i2c1_scl 0 iod h h 0 vdds yes 4 pu/ pd open drain k21 i2c1_sda 0 iod h h 0 vdds yes 4 pu/ pd open drain ac15 i2c2_scl 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_168 4 io safe_mode 7 ac14 i2c2_sda 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_183 4 io safe_mode 7 ac13 i2c3_scl 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_184 4 io safe_mode 7 ac12 i2c3_sda 0 iod h h 7 vdds yes 4 pu/ pd open drain gpio_185 4 io safe_mode 7 y16 i2c4_scl 0 iod h h 0 vdds yes 4 pu/ pd open drain sys_ nvmode1 1 o safe_mode 7 y15 i2c4_sda 0 iod h h 0 vdds yes 4 pu/ pd open drain sys_ nvmode2 1 o safe_mode 7 a24 hdq_sio 0 iod h h 7 vdds yes 4 pu/ pd lvcmos sys_altclk 1 i i2c2_sccbe 2 o i2c3_sccbe 3 o gpio_170 4 io safe_mode 7 t5 mcspi1_clk 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat4 1 io gpio_171 4 io safe_mode 7 r4 mcspi1_ simo 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat5 1 io gpio_172 4 io safe_mode 7 t4 mcspi1_ somi 0 io pgm l 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat6 1 io gpio_173 4 io safe_mode 7 t6 mcspi1_cs0 0 io pgm h 7 vdds yes 4 (2) pu/ pd lvcmos mmc2_dat7 1 io gpio_174 4 io terminal description 62 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] safe_mode 7 r5 mcspi1_cs3 0 o h h 7 vdds yes 4 pu/ pd lvcmos hsusb2_tll_ data2 2 io hsusb2_ data2 3 io gpio_177 4 io mm2_txdat 5 io safe_mode 7 n5 mcspi2_clk 0 io l l 7 vdds yes 4 pu/ pd lvcmos hsusb2_tll_ data7 2 io hsusb2_ data7 3 o gpio_178 4 io safe_mode 7 n4 mcspi2_ simo 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt9_pwm_evt 1 io hsusb2_tll_ data4 2 io hsusb2_ data4 3 i gpio_179 4 io safe_mode 7 n3 mcspi2_ somi 0 io l l 7 vdds yes 4 pu/ pd lvcmos gpt10_pwm_evt 1 io hsusb2_tll_ data5 2 io hsusb2_ data5 3 o gpio_180 4 io safe_mode 7 m5 mcspi2_cs0 0 io h h 7 vdds yes 4 pu/ pd lvcmos gpt11_pwm_evt 1 io hsusb2_tll_ data6 2 io hsusb2_ data6 3 o gpio_181 4 io safe_mode 7 m4 mcspi2_cs1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpt8_pwm_evt 1 io hsusb2_tll_ data3 2 io hsusb2_ data3 3 io gpio_182 4 io mm2_txen_n 5 io safe_mode 7 aa16 sys_32k 0 i z i na vdds yes na na lvcmos ad15 sys_xtalin 0 i z i na vdds yes na lvcmos ad14 sys_xtalout 0 o z o na vdds yes na lvcmos y13 sys_clkreq 0 io 0 1 0 vdds yes 4 pu/ pd lvcmos gpio_1 4 io safe_mode 7 w16 sys_nirq 0 i h h 7 vdds yes 4 pu/ pd lvcmos gpio_0 4 io safe_mode 7 aa10 sys_ nrespwron 0 i z i na vdds yes na na lvcmos y10 sys_ nreswarm 0 iod 0 1 (pu) 0 vdds yes 4 pu/ pd lvcmos gpio_30 4 io safe_mode 7 ab12 sys_boot0 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_2 4 io safe_mode 7 submit documentation feedback terminal description 63 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] ac16 sys_boot1 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_3 4 io safe_mode 7 ad17 sys_boot2 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_4 4 io safe_mode 7 ad18 sys_boot3 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_5 4 io safe_mode 7 ac17 sys_boot4 0 i z z 0 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat2 1 o gpio_6 4 io safe_mode 7 ab16 sys_boot5 0 i z z 0 vdds yes 4 pu/ pd lvcmos mmc2_dir_dat3 1 o gpio_7 4 io safe_mode 7 aa15 sys_boot6 0 i z z 0 vdds yes 4 pu/ pd lvcmos gpio_8 4 io safe_mode 7 ad23 sys_off_ mode 0 o 0 l 7 vdds yes 4 pu/ pd lvcmos gpio_9 4 io safe_mode 7 y7 sys_clkout1 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_10 4 io safe_mode 7 aa6 sys_clkout2 0 o l l 7 vdds yes 4 pu/ pd lvcmos gpio_186 4 io safe_mode 7 a1 sys_ ipmcsws 0 ai z ai na vdds na na na analog a2 sys_ opmcsws 0 ao 0 ao na vdds no na na lvcmos ab7 jtag_ntrst 0 i l l 0 vdds yes na pu/ pd lvcmos ab6 jtag_tck 0 i l l 0 vdds yes na pu/ pd lvcmos aa7 jtag_rtck 0 o l 0 0 vdds yes 4 pu/ pd lvcmos aa9 jtag_tms_tmsc 0 io h h 0 vdds yes 4 pu/ pd lvcmos ab10 jtag_tdi 0 i h h 0 vdds yes na pu/ pd lvcmos ab9 jtag_tdo 0 o l z 0 vdds yes 4 pu/ pd lvcmos ac24 jtag_emu0 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_11 4 io safe_mode 7 ad24 jtag_emu1 0 io h h 0 vdds yes 4 pu/ pd lvcmos gpio_31 4 io safe_mode 7 ac1 etk_clk 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcbsp5_ clkx 1 io mmc3_clk 2 o hsusb1_stp 3 o gpio_12 4 io mm1_rxdp 5 io hsusb1_tll_stp 6 i ad3 etk_ctl 0 o h h 4 vdds yes 4 pu/ pd lvcmos mmc3_cmd 2 io hsusb1_clk 3 o gpio_13 4 io terminal description 64 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] hsusb1_tll_clk 6 o ad6 etk_d0 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ simo 1 io mmc3_dat4 2 io hsusb1_ data0 3 io gpio_14 4 io mm1_rxrcv 5 io hsusb1_tll_ data0 6 io ac6 etk_d1 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_ somi 1 io hsusb1_ data1 3 io gpio_15 4 io mm1_txse0 5 io hsusb1_tll_ data1 6 io ac7 etk_d2 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs0 1 io hsusb1_ data2 3 io gpio_16 4 io mm1_txdat 5 io hsusb1_tll_data2 6 io ad8 etk_d3 0 o h h 4 vdds yes 4 pu/ pd lvcmos mcspi3_clk 1 io mmc3_dat3 2 io hsusb1_ data7 3 io gpio_17 4 io hsusb1_tll_ data7 6 io ac5 etk_d4 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dr 1 i mmc3_dat0 2 io hsusb1_ data4 3 io gpio_18 4 io hsusb1_tll_ data4 6 io ad2 etk_d5 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_fsx 1 io mmc3_dat1 2 io hsusb1_ data5 3 io gpio_19 4 io hsusb1_tll_ data5 6 io ac8 etk_d6 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcbsp5_dx 1 io mmc3_dat2 2 io hsusb1_ data6 3 io gpio_20 4 io hsusb1_tll_ data6 6 io ad9 etk_d7 0 o l l 4 vdds yes 4 pu/ pd lvcmos mcspi3_cs1 1 o mmc3_dat7 2 io hsusb1_ data3 3 io gpio_21 4 io mm1_txen_n 5 io hsusb1_tll_ data3 6 io submit documentation feedback terminal description 65 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-3. ball characteristics (cus pkg.) (continued) ball pin mode [4] type [5] ball ball reset power [9] hys buffer pull io bottom [1] name [3] reset reset rel. [10] strength u/d cell [13] state [6] rel. mode [8] (ma) [11] type [12] state [7] ac4 etk_d8 0 o l l 4 vdds yes 4 pu/ pd lvcmos sys_drm_ 1 o msecure mmc3_dat6 2 io hsusb1_dir 3 i gpio_22 4 io hsusb1_tll_dir 6 o ad5 etk_d9 0 o l l 4 vdds yes 4 pu/ pd lvcmos sys_secure_indic 1 o ator mmc3_dat5 2 io hsusb1_nxt 3 i gpio_23 4 io mm1_rxdm 5 io hsusb1_tll_nxt 6 o ac3 etk_d10 0 o l l 4 vdds yes 4 pu/ pd lvcmos uart1_rx 2 i hsusb2_clk 3 o gpio_24 4 io hsusb2_tll_clk 6 o ac9 etk_d11 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_stp 3 o gpio_25 4 io mm2_rxdp 5 io hsusb2_tll_stp 6 i ac10 etk_d12 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_dir 3 i gpio_26 4 io hsusb2_tll_dir 6 o ad11 etk_d13 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_nxt 3 i gpio_27 4 io mm2_rxdm 5 io hsusb2_tll_nxt 6 o ac11 etk_d14 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data0 3 io gpio_28 4 io mm2_rxrcv 5 io hsusb2_tll_ data0 6 io ad12 etk_d15 0 o l l 4 vdds yes 4 pu/ pd lvcmos hsusb2_ data1 3 io gpio_29 4 io mm2_txse0 5 io hsusb2_tll_ data1 6 io terminal description 66 submit documentation feedback product preview
2.3 multiplexing characteristics omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-4 through table 2-6 provide a description of the omap35 15/03 multiplexing on the cbb, cbc, and cus packages, respectively. note: table 2-4 and table 2-6 do not take into account subsystem pin multiplexing options. subsystem pin multiplexing options are described in section 2.4 , signal description. table 2-4. multiplexing characteristics (cbb pkg.) (1) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top d6 j2 sdrc_d0 - - - - - - - c6 j1 sdrc_d1 - - - - - - - b6 g2 sdrc_d2 - - - - - - - c8 g1 sdrc_d3 - - - - - - - c9 f2 sdrc_d4 - - - - - - - a7 f1 sdrc_d5 - - - - - - - b9 d2 sdrc_d6 - - - - - - - a9 d1 sdrc_d7 - - - - - - - c14 b13 sdrc_d8 - - - - - - - b14 a13 sdrc_d9 - - - - - - - c15 b14 sdrc_d10 - - - - - - - b16 a14 sdrc_d11 - - - - - - - d17 b16 sdrc_d12 - - - - - - - c17 a16 sdrc_d13 - - - - - - - b17 b19 sdrc_d14 - - - - - - - d18 a19 sdrc_d15 - - - - - - - d11 b3 sdrc_d16 - - - - - - - b10 a3 sdrc_d17 - - - - - - - c11 b5 sdrc_d18 - - - - - - - d12 a5 sdrc_d19 - - - - - - - c12 b8 sdrc_d20 - - - - - - - a11 a8 sdrc_d21 - - - - - - - b13 b9 sdrc_d22 - - - - - - - d14 a9 sdrc_d23 - - - - - - - c18 b21 sdrc_d24 - - - - - - - a19 a21 sdrc_d25 - - - - - - - b19 d22 sdrc_d26 - - - - - - - b20 d23 sdrc_d27 - - - - - - - d20 e22 sdrc_d28 - - - - - - - a21 e23 sdrc_d29 - - - - - - - b21 g22 sdrc_d30 - - - - - - - c21 g23 sdrc_d31 - - - - - - - h9 ab21 sdrc_ba0 - - - - - - - h10 ac21 sdrc_ba1 - - - - - - - a4 n22 sdrc_a0 - - - - - - - b4 n 23 sdrc_a1 - - - - - - - b3 p22 sdrc_a2 - - - - - - - c5 p23 sdrc_a3 - - - - - - - c4 r22 sdrc_a4 - - - - - - - (1) na in table stands for not applicable. submit documentation feedback terminal description 67 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top d5 r23 sdrc_a5 - - - - - - - c3 t22 sdrc_a6 - - - - - - - c2 t23 sdrc_a7 - - - - - - - c1 u22 sdrc_a8 - - - - - - - d4 u23 sdrc_a9 - - - - - - - d3 v22 sdrc_a10 - - - - - - - d2 v23 sdrc_a11 - - - - - - - d1 w22 sdrc_a12 - - - - - - - e2 w23 sdrc_a13 - - - - - - - e1 y22 sdrc_a14 - - - - - - - h11 m22 sdrc_ncs0 - - - - - - - h12 m23 sdrc_ncs1 - - - - - - - a13 a11 sdrc_clk - - - - - - - a14 b11 sdrc_nclk - - - - - - - h16 j22 sdrc_cke0 - - - - - - safe_mode h17 j23 sdrc_cke1 - - - - - - safe_mode h14 l23 sdrc_nras - - - - - - - h13 l22 sdrc_ncas - - - - - - - h15 k23 sdrc_nwe - - - - - - - b7 c1 sdrc_dm0 - - - - - - - a16 a17 sdrc_dm1 - - - - - - - b11 a6 sdrc_dm2 - - - - - - - c20 a20 sdrc_dm3 - - - - - - - a6 c2 sdrc_dqs0 - - - - - - - a17 b17 sdrc_dqs1 - - - - - - - a10 b6 sdrc_dqs2 - - - - - - - a20 b20 sdrc_dqs3 - - - - - - - n4 ac15 gpmc_a1 - - - gpio_34 - - safe_mode m4 ab15 gpmc_a2 - - - gpio_35 - - safe_mode l4 ac16 gpmc_a3 - - - gpio_36 - - safe_mode k4 ab16 gpmc_a4 - - - gpio_37 - - safe_mode t3 ac17 gpmc_a5 - - - gpio_38 - - safe_mode r3 ab17 gpmc_a6 - - - gpio_39 - - safe_mode n3 ac18 gpmc_a7 - - - gpio_40 - - safe_mode m3 ab18 gpmc_a8 - - - gpio_41 - - safe_mode l3 ac19 gpmc_a9 sys_ - - gpio_42 - - safe_mode ndmareq2 k3 ab19 gpmc_a10 sys_ - - gpio_43 - - safe_mode ndmareq3 k1 m2 gpmc_d0 - - - - - - - l1 m1 gpmc_d1 - - - - - - - l2 n2 gpmc_d2 - - - - - - - p2 n 1 gpmc_d3 - - - - - - - t1 r2 gpmc_d4 - - - - - - - v1 r1 gpmc_d5 - - - - - - - v2 t2 gpmc_d6 - - - - - - - w2 t1 gpmc_d7 - - - - - - - terminal description 68 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top h2 ab3 gpmc_d8 - - - gpio_44 - - safe_mode k2 ac3 gpmc_d9 - - - gpio_45 - - safe_mode p1 ab4 gpmc_d10 - - - gpio_46 - - safe_mode r1 ac4 gpmc_d11 - - - gpio_47 - - safe_mode r2 ab6 gpmc_d12 - - - gpio_48 - - safe_mode t2 ac6 gpmc_d13 - - - gpio_49 - - safe_mode w1 ab7 gpmc_d14 - - - gpio_50 - - safe_mode y1 ac7 gpmc_d15 - - - gpio_51 - - safe_mode g4 y2 gpmc_ncs0 - - - - - - - h3 y1 gpmc_ncs1 - - - gpio_52 - - safe_mode v8 na gpmc_ncs2 - - - gpio_53 - - safe_mode u8 na gpmc_ncs3 sys_ - - gpio_54 - - safe_mode ndmareq0 t8 na gpmc_ncs4 sys_ mcbsp4_clkx gpt9_pwm_ gpio_55 - - safe_mode ndmareq1 evt r8 na gpmc_ncs5 sys_ mcbsp4_dr gpt10_pwm_ gpio_56 - - safe_mode ndmareq2 evt p8 na gpmc_ncs6 sys_ mcbsp4_dx gpt11_pwm_ gpio_57 - - safe_mode ndmareq3 evt n8 na gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ gpio_58 - - safe_mode evt t4 w2 gpmc_clk - - - gpio_59 - - safe_mode f3 w1 gpmc_nadv_ - - - - - - - ale g2 v2 gpmc_noe - - - - - - - f4 v1 gpmc_nwe - - - - - - - g3 ac12 gpmc_nbe0_ - - - gpio_60 - - safe_mode cle u3 na gpmc_nbe1 - - - gpio_61 - - safe_mode h1 ab10 gpmc_nwp - - - gpio_62 - - safe_mode m8 ab12 gpmc_wait0 - - - - - - - l8 ac10 gpmc_wait1 - - - gpio_63 - - safe_mode k8 na gpmc_wait2 - - - gpio_64 - - safe_mode j8 na gpmc_wait3 sys_ - - gpio_65 - - safe_mode ndmareq1 d28 na dss_pclk - - - gpio_66 - - safe_mode d26 na dss_hsync - - - gpio_67 - - safe_mode d27 na dss_vsync - - - gpio_68 - - safe_mode e27 na dss_acbias - - - gpio_69 - - safe_mode ag22 na dss_data0 - uart1_cts - gpio_70 - - safe_mode ah22 na dss_data1 - uart1_rts - gpio_71 - - safe_mode ag23 na dss_data2 - - - gpio_72 - - safe_mode ah23 na dss_data3 - - - gpio_73 - - safe_mode ag24 na dss_data4 - uart3_rx_irrx - gpio_74 - - safe_mode ah24 na dss_data5 - uart3_tx_irtx - gpio_75 - - safe_mode e26 na dss_data6 - uart1_tx - gpio_76 - - safe_mode f28 na dss_data7 - uart1_rx - gpio_77 - - safe_mode f27 na dss_data8 - - - gpio_78 - - safe_mode g26 na dss_data9 - - - gpio_79 - - safe_mode submit documentation feedback terminal description 69 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top ad28 na dss_data10 - - - gpio_80 - - safe_mode ad27 na dss_data11 - - - gpio_81 - - safe_mode ab28 na dss_data12 - - - gpio_82 - - safe_mode ab27 na dss_data13 - - - gpio_83 - - safe_mode aa28 na dss_data14 - - - gpio_84 - - safe_mode aa27 na dss_data15 - - - gpio_85 - - safe_mode g25 na dss_data16 - - - gpio_86 - - safe_mode h27 na dss_data17 - - - gpio_87 - - safe_mode h26 na dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode h25 na dss_data19 - mcspi3_simo dss_data1 gpio_89 - - safe_mode e28 na dss_data20 - mcspi3_somi dss_data2 gpio_90 - - safe_mode j26 na dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode ac27 na dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode ac28 na dss_data23 - - dss_data5 gpio_93 - - safe_mode w28 na tv_out2 - - - - - - - y28 na tv_out1 - - - - - - - y27 na tv_vfb1 - - - - - - - w27 na tv_vfb2 - - - - - - - w26 na tv_vref - - - - - - - a24 na cam_hs - - - gpio_94 - - safe_mode a23 na cam_vs - - - gpio_95 - - safe_mode c25 na cam_xclka - - - gpio_96 - - safe_mode c27 na cam_pclk - - - gpio_97 - - safe_mode c23 na cam_fld - cam_global_ - gpio_98 - - safe_mode reset ag17 na cam_d0 - - - gpio_99 - - safe_mode ah17 na cam_d1 - - - gpio_100 - - safe_mode b24 na cam_d2 - - - gpio_101 - - safe_mode c24 na cam_d3 - - - gpio_102 - - safe_mode d24 na cam_d4 - - - gpio_103 - - safe_mode a25 na cam_d5 - - - gpio_104 - - safe_mode k28 na cam_d6 - - - gpio_105 - - safe_mode l28 na cam_d7 - - - gpio_106 - - safe_mode k27 na cam_d8 - - - gpio_107 - - safe_mode l27 na cam_d9 - - - gpio_108 - - safe_mode b25 na cam_d10 - - - gpio_109 - - safe_mode c26 na cam_d11 - - - gpio_110 - - safe_mode b26 na cam_xclkb - - - gpio_111 - - safe_mode b23 na cam_wen - cam_shutter - gpio_167 - - safe_mode d25 na cam_strobe - - - gpio_126 - - safe_mode ag19 na - - - - gpio_112 - - safe_mode ah19 na - - - - gpio_113 - - safe_mode ag18 na - - - - gpio_114 - - safe_mode ah18 na - - - - gpio_115 - - safe_mode p21 na mcbsp2_fsx - - - gpio_116 - - safe_mode n21 na mcbsp2_clkx - - - gpio_117 - - safe_mode r21 na mcbsp2_dr - - - gpio_118 - - safe_mode terminal description 70 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top m21 na mcbsp2_dx - - - gpio_119 - - safe_mode n28 n a mmc1_clk - - - gpio_120 - - safe_mode m27 na mmc1_cmd - - - gpio_121 - - safe_mode n27 na mmc1_dat0 - - - gpio_122 - - safe_mode n26 na mmc1_dat1 - - - gpio_123 - - safe_mode n25 na mmc1_dat2 - - - gpio_124 - - safe_mode p28 na mmc1_dat3 - - - gpio_125 - - safe_mode p27 na mmc1_dat4 - - - gpio_126 - - safe_mode p26 na mmc1_dat5 - - - gpio_127 - - safe_mode r27 na mmc1_dat6 - - - gpio_128 - - safe_mode r25 na mmc1_dat7 - - - gpio_129 - - safe_mode ae2 na mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode ag5 na mmc2_cmd mcspi3_simo - - gpio_131 - - safe_mode ah5 na mmc2_dat0 mcspi3_somi - - gpio_132 - - safe_mode ah4 na mmc2_dat1 - - - gpio_133 - - safe_mode ag4 na mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode af4 na mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode ae4 na mmc2_dat4 mmc2_dir_ - mmc3_dat0 gpio_136 - - safe_mode dat0 ah3 na mmc2_dat5 mmc2_dir_ cam_global_ mmc3_dat1 gpio_137 hsusb3_tll_ mm3_rxdp safe_mode dat1 reset stp af3 na mmc2_dat6 mmc2_dir_ cam_shutter mmc3_dat2 gpio_138 hsusb3_tll_ - safe_mode cmd dir ae3 na mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 hsusb3_tll_ mm3_rxdm safe_mode nxt af6 na mcbsp3_dx uart2_cts - - gpio_140 hsusb3_tll_ - safe_mode data4 ae6 na mcbsp3_dr uart2_rts - - gpio_141 hsusb3_tll_ - safe_mode data5 af5 na mcbsp3_clkx uart2_tx - - gpio_142 hsusb3_tll_ - safe_mode data6 ae5 na mcbsp3_fsx uart2_rx - - gpio_143 hsusb3_tll_ - safe_mode data7 ab2 na uart2_cts mcbsp3_dx gpt9_pwm_ - gpio_144 - - safe_mode evt ab25 na uart2_rts mcbsp3_dr gpt10_pwm_ - gpio_145 - - safe_mode evt aa25 na uart2_tx mcbsp3_clkx gpt11_pwm_ - gpio_146 - - safe_mode evt ad25 na uart2_rx mcbsp3_fsx gpt8_pwm_ - gpio_147 - - safe_mode evt aa8 na uart1_tx - - - gpio_148 - - safe_mode aa9 na uart1_rts - - - gpio_149 - - safe_mode w8 na uart1_cts - - - gpio_150 hsusb3_tll_ - safe_mode clk y8 na uart1_rx - mcbsp1_clkr mcspi4_clk gpio_151 - - safe_mode ae1 na mcbsp4_clkx - - - gpio_152 hsusb3_tll_ mm3_txse0 safe_mode data1 ad1 na mcbsp4_dr - - - gpio_153 hsusb3_tll_ mm3_rxrcv safe_mode data0 submit documentation feedback terminal description 71 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top ad2 na mcbsp4_dx - - - gpio_154 hsusb3_tll_ mm3_txdat safe_mode data2 ac1 na mcbsp4_fsx - - - gpio_155 hsusb3_tll_ mm3_txen_n safe_mode data3 y21 na mcbsp1_clkr mcspi4_clk - - gpio_156 - - safe_mode aa21 na mcbsp1_fsr - cam_global_ - gpio_157 - - safe_mode reset v21 na mcbsp1_dx mcspi4_simo mcbsp3_dx - gpio_158 - - safe_mode u21 na mcbsp1_dr mcspi4_somi mcbsp3_dr - gpio_159 - - safe_mode t21 na mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode k26 na mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode w21 na mcbsp1_clkx - mcbsp3_clkx - gpio_162 - - safe_mode h18 na uart3_cts_rct - - - gpio_163 - - safe_mode x h19 na uart3_rts_sd - - - gpio_164 - - safe_mode h20 n a uart3_rx_irrx - - - gpio_165 - - safe_mode h21 na uart3_tx_irtx - - - gpio_166 - - safe_mode t28 na hsusb0_clk - - - gpio_120 - - safe_mode t25 na hsusb0_stp - - - gpio_121 - - safe_mode r28 na hsusb0_dir - - - gpio_122 - - safe_mode t26 na hsusb0_nxt - - - gpio_124 - - safe_mode t27 na hsusb0_ - uart3_tx_irtx - gpio_125 - - safe_mode data0 u28 na hsusb0_ - uart3_rx_irrx - gpio_130 - - safe_mode data1 u27 na hsusb0_ - uart3_rts_sd - gpio_131 - - safe_mode data2 u26 na hsusb0_ - uart3_cts_ - gpio_169 - - safe_mode data3 rctx u25 na hsusb0_ - - - gpio_188 - - safe_mode data4 v28 na hsusb0_ - - - gpio_189 - - safe_mode data5 v27 na hsusb0_ - - - gpio_190 - - safe_mode data6 v26 na hsusb0_ - - - gpio_191 - - safe_mode data7 k21 na i2c1_scl - - - - - - - j21 na i2c1_sda - - - - - - - af15 na i2c2_scl - - - gpio_168 - - safe_mode ae15 na i2c2_sda - - - gpio_183 - - safe_mode af14 na i2c3_scl - - - gpio_184 - - safe_mode ag14 na i2c3_sda - - - gpio_185 - - safe_mode ad26 na i2c4_scl sys_ - - - - - safe_mode nvmode1 ae26 na i2c4_sda sys_ - - - - - safe_mode nvmode2 j25 na hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode ab3 na mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode ab4 na mcspi1_simo mmc2_dat5 - - gpio_172 - - safe_mode aa4 na mcspi1_somi mmc2_dat6 - - gpio_173 - - safe_mode terminal description 72 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top ac2 na mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode ac3 na mcspi1_cs1 - - mmc3_cmd gpio_175 - - safe_mode ab1 na mcspi1_cs2 - - mmc3_clk gpio_176 - - safe_mode ab2 na mcspi1_cs3 - hsusb2_tll_ hsusb2_ gpio_177 mm2_txdat - safe_mode data2 data2 aa3 na mcspi2_clk - hsusb2_tll_ hsusb2_ gpio_178 - - safe_mode data7 data7 y2 na mcspi2_simo gpt9_pwm_ hsusb2_tll_ hsusb2_ gpio_179 - - safe_mode evt data4 data4 y3 na mcspi2_somi gpt10_pwm_ hsusb2_tll_ hsusb2_ gpio_180 - - safe_mode evt data5 data5 y4 na mcspi2_cs0 gpt11_pwm_ hsusb2_tll_ hsusb2_ gpio_181 - - safe_mode evt data6 data6 v3 na mcspi2_cs1 gpt8_pwm_ hsusb2_tll_ hsusb2_ gpio_182 mm2_txen_n - safe_mode evt data3 data3 ae25 na sys_32k - - - - - - - ae17 na sys_xtalin - - - - - - - af17 na sys_xtalout - - - - - - - af25 na sys_clkreq - - - gpio_1 - - safe_mode af26 na sys_nirq - - - gpio_0 - - safe_mode ah25 na sys_nrespwr - - - - - - - on af24 na sys_nreswar - - - gpio_30 - - safe_mode m ah26 na sys_boot0 - - - gpio_2 - - safe_mode ag26 na sys_boot1 - - - gpio_3 - - safe_mode ae14 na sys_boot2 - - - gpio_4 - - safe_mode af18 na sys_boot3 - - - gpio_5 - - safe_mode af19 na sys_boot4 mmc2_dir_ - - gpio_6 - - safe_mode dat2 ae21 na sys_boot5 mmc2_dir_ - - gpio_7 - - safe_mode dat3 af21 n a sys_boot6 - - - gpio_8 - - safe_mode af22 na sys_off_ - - - gpio_9 - - safe_mode mode ag25 na sys_clkout1 - - - gpio_10 - - safe_mode ae22 na sys_clkout2 - - - gpio_186 - - safe_mode b1 na sys_ipmcsws - - - - - - - a1 na sys_ - - - - - - - opmcsws aa17 na jtag_ntrst - - - - - - - aa13 na jtag_tck - - - - - - - aa12 na jtag_rtck - - - - - - - aa18 na jtag_tms_ - - - - - - - tmsc aa20 na jtag_tdi - - - - - - - aa19 na jtag_tdo - - - - - - - aa11 na jtag_emu0 - - - gpio_11 - - safe_mode aa10 na jtag_emu1 - - - gpio_31 - - safe_mode af10 na etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ - stp submit documentation feedback terminal description 73 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-4. multiplexing characteristics (cbb pkg.) (continued) ball ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom top ae10 na etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ - clk af11 na etk_d0 mcspi3_simo mmc3_dat4 hsusb1_ gpio_14 mm1_rxrcv hsusb1_tll_ - data0 data0 ag12 na etk_d1 mcspi3_somi - hsusb1_ gpio_15 mm1_txse0 hsusb1_tll_ - data1 data1 ah12 na etk_d2 mcspi3_cs0 - hsusb1_ gpio_16 mm1_txdat hsusb1_tll_ - data2 data2 ae13 na etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ gpio_17 - hsusb1_tll_ - data7 data7 ae11 na etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ gpio_18 - hsusb1_tll_ - data4 data4 ah9 na etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ gpio_19 - hsusb1_tll_ - data5 data5 af13 na etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ gpio_20 - hsusb1_tll_ - data6 data6 ah14 na etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ gpio_21 mm1_txen_n hsusb1_tll_ - data3 data3 af9 na etk_d8 sys_drm_ mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ - msecure dir ag9 na etk_d9 sys_secure_ mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ - indicator nxt ae7 na etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ - clk af7 na etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ - stp ag7 na etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ - dir ah7 na etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ - nxt ag8 na etk_d14 - - hsusb2_ gpio_28 mm2_rxrcv hsusb2_tll_ - data0 data0 ah8 na etk_d15 - - hsusb2_ gpio_29 mm2_txse0 hsusb2_tll_ - data1 data1 table 2-5. multiplexing characteristics (cbc pkg.) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom ae16 - cam_d0 - - - - gpio_99 - safe_mode ae15 - cam_d1 - - - - gpio_100 - safe_mode ad17 - - - - - - gpio_112 - safe_mode ae18 - - - - - - gpio_114 - safe_mode ad16 - - - - - - gpio_113 - safe_mode ae17 - - - - - - gpio_115 - safe_mode - g20 sdrc_a0 - - - - - - - - k20 sdrc_a1 - - - - - - - - j20 sdrc_a2 - - - - - - - - j21 sdrc_a3 - - - - - - - - u21 sdrc_a4 - - - - - - - - r20 sdrc_a5 - - - - - - - - m21 sdrc_a6 - - - - - - - - m20 sdrc_a7 - - - - - - - terminal description 74 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom - n20 sdrc_a8 - - - - - - - - k21 sdrc_a9 - - - - - - - - y16 sdrc_a10 - - - - - - - - n21 sdrc_a11 - - - - - - - - r21 sdrc_a12 - - - - - - - - aa15 sdrc_a13 - - - - - - - - y12 sdrc_a14 - - - - - - - - aa18 sdrc_ba0 - - - - - - - - v20 sdrc_ba1 - - - - - - - - y15 sdrc_cke0 - - - - - - safe_mode - y13 sdrc_cke1 - - - - - - safe_mode - a12 sdrc_clk - - - - - - - - d1 sdrc_d0 - - - - - - - - g1 sdrc_d1 - - - - - - - - g2 sdrc_d2 - - - - - - - - e1 sdrc_d3 - - - - - - - - d2 sdrc_d4 - - - - - - - - e2 sdrc_d5 - - - - - - - - b3 sdrc_d6 - - - - - - - - b4 sdrc_d7 - - - - - - - - a10 sdrc_d8 - - - - - - - - b11 sdrc_d9 - - - - - - - - a11 sdrc_d10 - - - - - - - - b12 sdrc_d11 - - - - - - - - a16 sdrc_d12 - - - - - - - - a17 sdrc_d13 - - - - - - - - b17 sdrc_d14 - - - - - - - - b18 sdrc_d15 - - - - - - - - b7 sdrc_d16 - - - - - - - - a5 sdrc_d17 - - - - - - - - b6 sdrc_d18 - - - - - - - - a6 sdrc_d19 - - - - - - - - a8 sdrc_d20 - - - - - - - - b9 sdrc_d21 - - - - - - - - a9 sdrc_d22 - - - - - - - - b10 sdrc_d23 - - - - - - - - c21 sdrc_d24 - - - - - - - - d20 sdrc_d25 - - - - - - - - b19 sdrc_d26 - - - - - - - - c20 sdrc_d27 - - - - - - - - d21 sdrc_d28 - - - - - - - -- e20 sdrc_d29 - - - - - - - - e21 sdrc_d30 - - - - - - - - g21 sdrc_d31 - - - - - - - - h1 sdrc_dm0 - - - - - - - - a14 sdrc_dm1 - - - - - - - submit documentation feedback terminal description 75 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom - a4 sdrc_dm2 - - - - - - - a18 sdrc_dm3 - - - - - - - - - c2 sdrc_dqs0 - - - - - - - - b15 sdrc_dqs1 - - - - - - - - b8 sdrc_dqs2 - - - - - - - - a19 sdrc_dqs3 - - - - - - - - u20 sdrc_ncas - - - - - - - - b13 sdrc_nclk - - - - - - - - t21 sdrc_ncs0 - - - - - - - - t20 sdrc_ncs1 - - - - - - - - v21 sdrc_nras - - - - - - - - y18 sdrc_nwe - - - - - - - ae21 - dss_data0 dx0 uart1_cts - gpio_70 - - safe_mode ae22 - dss_data1 dy0 uart1_rts - gpio_71 - - safe_mode ae23 - dss_data2 dx1 - - gpio_72 - - safe_mode ae24 - dss_data3 dy1 - - gpio_73 - - safe_mode ac26 - dss_data10 - - - gpio_80 - - safe_mode ad26 - dss_data11 - - - gpio_81 - - safe_mode aa25 - dss_data12 - - - gpio_82 - - safe_mode y25 - dss_data13 - - - gpio_83 - - safe_mode aa26 - dss_data14 - - - gpio_84 - - safe_mode ab26 - dss_data15 - - - gpio_85 - - safe_mode f25 - dss_data20 - mcspi3_so dss_data2 gpio_90 - - safe_mode mi ac25 - dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode ab25 - dss_data23 - - dss_data5 gpio_93 - - safe_mode g25 - dss_pclk - - - gpio_66 hw_dbg12 - safe_mode j2 - gpmc_a1 - - - gpio_34 - - safe_mode h1 - gpmc_a2 - - - gpio_35 - - safe_mode h2 - gpmc_a3 - - - gpio_36 - - safe_mode g2 - gpmc_a4 - - - gpio_37 - - safe_mode f1 - gpmc_a5 - - - gpio_38 - - safe_mode f2 - gpmc_a6 - - - gpio_39 - - safe_mode e1 - gpmc_a7 - - - gpio_40 - - safe_mode e2 - gpmc_a8 - - - gpio_41 - - safe_mode d1 - gpmc_a9 sys_ndmare - - gpio_42 - - safe_mode q2 d2 - gpmc_a10 sys_ndmare - - gpio_43 - - safe_mode q3 n1 - gpmc_clk - - - gpio_59 - - safe_mode aa2 - gpmc_d0 - - - - - - - aa1 - gpmc_d1 - - - - - - - ac2 - gpmc_d2 - - - - - - - ac1 - gpmc_d3 - - - - - - - ae5 - gpmc_d4 - - - - - - - ad6 - gpmc_d5 - - - - - - - ad5 - gpmc_d6 - - - - - - - terminal description 76 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom ac5 - gpmc_d7 - - - - - - - v1 - gpmc_d8 - - - gpio_44 - - safe_mode y1 - gpmc_d9 - - - gpio_45 - - safe_mode t1 - gpmc_d10 - - - gpio_46 - - safe_mode u2 - gpmc_d11 - - - gpio_47 - - safe_mode u1 - gpmc_d12 - - - gpio_48 - - safe_mode p1 - gpmc_d13 - - - gpio_49 - - safe_mode l2 - gpmc_d14 - - - gpio_50 - - safe_mode m2 - gpmc_d15 - - - gpio_51 - - safe_mode ad10 - gpmc_nadv - - - - - - - _ale k2 - gpmc_nbe0 - - - gpio_60 - - safe_mode _cle j1 - gpmc_nbe1 - - - gpio_61 - - safe_mode ad8 - gpmc_ncs0 - - - - - - - ad1 - gpmc_ncs1 - - - gpio_52 - - safe_mode a3 - gpmc_ncs2 - - - gpio_53 - - safe_mode b6 - gpmc_ncs3 sys_ndmare - - gpio_54 - - safe_mode q0 b4 - gpmc_ncs4 sys_ndmare mcbsp4_clk gpt9_pwm_ gpio_55 - - safe_mode q1 x evt c4 - gpmc_ncs5 sys_ndmare mcbsp4_dr gpt10_pwm gpio_56 - - safe_mode q2 _evt b5 - gpmc_ncs6 sys_ndmare mcbsp4_dx gpt11_pwm gpio_57 - - safe_mode q3 _evt c5 - gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ gpio_58 - - safe_mode evt n2 - gpmc_noe - - - - - - - m1 - gpmc_nwe - - - - - - - ac6 - gpmc_nwp - - - gpio_62 - - safe_mode ac11 - gpmc_wait0 - - - - - - - ac8 - gpmc_wait1 - - - gpio_63 - - safe_mode b3 - gpmc_wait2 - - - gpio_64 - - safe_mode c6 - gpmc_wait3 sys_ndmare - - gpio_65 - - safe_mode q1 w19 - hsusb0_clk - - - gpio_120 - - safe_mode v20 - hsusb0_dat - uart3_tx_irtx - gpio_125 - - safe_mode a0 y20 - hsusb0_dat - uart3_rx_irr - gpio_130 - - safe_mode a1 x v18 - hsusb0_dat - uart3_rts_s - gpio_131 - - safe_mode a2 d w20 - hsusb0_dat - uart3_cts_rc - gpio_169 - - safe_mode a3 tx w17 - hsusb0_dat - - - gpio_188 - - safe_mode a4 y18 - hsusb0_dat - - - gpio_189 - - safe_mode a5 y19 - hsusb0_dat - - - gpio_190 - - safe_mode a6 submit documentation feedback terminal description 77 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom y17 - hsusb0_dat - - - gpio_191 - - safe_mode a7 v19 - hsusb0_dir - - - gpio_122 - - safe_mode w18 - hsusb0_nxt - - - gpio_124 - - safe_mode u20 - hsusb0_stp - - - gpio_121 - - safe_mode u15 - jtag_ntrst - - - - - - - w13 - jtag_rtck - - - - - - - v14 - jtag_tck - - - - - - - u16 - jtag_tdi - - - - - - - y13 - jtag_tdo - - - - - - - v15 - jtag_tms_tm - - - - - - - sc ae19 - vdd_dsi - - - - - - - k20 - vdd_sram_c - - - - - - - ore n9 - vdd_sram_ - - - - - - - mpu_iva k14 - vdd_wkup - - - - - - - - vdd_sram_e - - - - - - - mu n19 - mmc1_clk ms_clk - - gpio_120 - - safe_mode l18 - mmc1_cmd ms_bs - - gpio_121 - - safe_mode m19 - mmc1_dat0 ms_dat0 - - gpio_122 - - safe_mode m18 - mmc1_dat1 ms_dat1 - - gpio_123 - - safe_mode k18 - mmc1_dat2 ms_dat2 - - gpio_124 - - safe_mode n20 - mmc1_dat3 ms_dat3 - - gpio_125 - - safe_mode m20 - mmc1_dat4 - - - gpio_126 - - safe_mode p17 - mmc1_dat5 - - - gpio_127 - - safe_mode p18 - mmc1_dat6 - - - gpio_128 - - safe_mode p19 - mmc1_dat7 - - - gpio_129 - - safe_mode j25 - i2c1_scl - - - - - - - j24 - i2c1_sda - - - - - - - c2 - i2c2_scl - - - gpio_168 - - safe_mode c1 - i2c2_sda - - - gpio_183 - - safe_mode ab4 - i2c3_scl - - - gpio_184 - - safe_mode ac4 - i2c3_sda - - - gpio_185 - - safe_mode u19 - mcbsp1_clk mcspi4_clk - - gpio_156 - - safe_mode r t17 - mcbsp1_clk - mcbsp3_clk - gpio_162 - - safe_mode x x t20 - mcbsp1_dr mcspi4_so mcbsp3_dr - gpio_159 - - safe_mode mi u17 - mcbsp1_dx mcspi4_sim mcbsp3_dx - gpio_158 - - safe_mode o v17 - mcbsp1_fsr - cam_global - gpio_157 - - safe_mode _reset p20 - mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode r18 - mcbsp2_clk - - - gpio_117 - - safe_mode x t18 - mcbsp2_dr - - - gpio_118 - - safe_mode terminal description 78 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom r19 - mcbsp2_dx - - - gpio_119 - - safe_mode u18 - mcbsp2_fsx - - - gpio_116 - - safe_mode p9 - mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode r7 - mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode r9 - mcspi1_cs2 - - mmc3_clk gpio_176 - - safe_mode p8 - mcspi1_sim mmc2_dat5 - - gpio_172 - - safe_mode o p7 - mcspi1_so mmc2_dat6 - - gpio_173 - - safe_mode mi w10 - mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode r10 - mmc2_cmd mcspi3_sim - - gpio_131 - - safe_mode o t10 - mmc2_dat0 mcspi3_so - - gpio_132 - - safe_mode mi t9 - mmc2_dat1 - - - gpio_133 - - safe_mode u10 - mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode u9 - mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode v10 - mmc2_dat4 mmc2_dir_d - mmc3_dat0 gpio_136 - - safe_mode at0 r2 - uart1_rts - - - gpio_149 - - safe_mode h3 - uart1_rx - mcbsp1_clk mcspi4_clk gpio_151 - - safe_mode r l4 - uart1_tx - - - gpio_148 - - safe_mode y24 - uart2_cts mcbsp3_dx gpt9_pwm_ - gpio_144 - - safe_mode evt aa24 - uart2_rts mcbsp3_dr gpt10_pwm - gpio_145 - - safe_mode _evt ad21 - uart2_rx mcbsp3_fsx gpt8_pwm_ - gpio_147 - - safe_mode evt ad22 - uart2_tx mcbsp3_clk gpt11_pwm - gpio_146 - - safe_mode x _evt f23 - uart3_cts_rc - - - gpio_163 - - safe_mode tx f24 - uart3_rts_s - - - gpio_164 - - safe_mode d h24 - uart3_rx_irr - - - gpio_165 - - safe_mode x g24 - uart3_tx_irtx - - - gpio_166 - - safe_mode j23 - hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode ad15 - i2c4_scl sys_nvmod - - - - - safe_mode e1 w16 - i2c4_sda sys_nvmod - - - - - safe_mode e2 f3 - sys_boot0 - - - gpio_2 - - safe_mode d3 - sys_boot1 - - - gpio_3 - - safe_mode c3 - sys_boot2 - - - gpio_4 - - safe_mode e3 - sys_boot3 - - - gpio_5 - - safe_mode e4 - sys_boot4 mmc2_dir_d - - gpio_6 - - safe_mode at2 g3 - sys_boot5 mmc2_dir_d - - gpio_7 - - safe_mode at3 d4 - sys_boot6 - - - gpio_8 - - safe_mode submit documentation feedback terminal description 79 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom ae14 - sys_clkout1 - - - gpio_10 - - safe_mode w11 - sys_clkout2 - - - gpio_186 - - safe_mode w15 - sys_clkreq - - - gpio_1 - - safe_mode v16 - sys_nirq - - - gpio_0 - - safe_mode v13 - sys_nrespw - - - - - - - ron ad7 - sys_nreswa - - - gpio_30 - - safe_mode rm v12 - sys_off_mo - - - gpio_9 - - safe_mode de af19 - sys_xtalin - - - - - - - d6 - bg_testout - - - - - - - n18 - pbias_mmc - - - - - - - 1 k23 - pbias_sim - - - - - - - b1 - sys_ipmcsw - - - - - - - s a2 - sys_opmcs - - - - - - - ws w26 - tv_out1 - - - - - - - v26 - tv_out2 - - - - - - - w25 - tv_vfb1 - - - - - - - u24 - tv_vfb2 - - - - - - - v23 - tv_vref - - - - - - - ae20 - sys_32k - - - - - - - a24 - cam_d2 - - - gpio_101 hw_dbg4 - safe_mode b24 - cam_d3 - - - gpio_102 hw_dbg5 - safe_mode d24 - cam_d4 - - - gpio_103 hw_dbg6 - safe_mode c24 - cam_d5 - - - gpio_104 hw_dbg7 - safe_mode d25 - cam_d10 - - - gpio_109 hw_dbg8 - safe_mode e26 - cam_d11 - - - gpio_110 hw_dbg9 - safe_mode b23 - cam_fld - cam_global - gpio_98 hw_dbg3 - safe_mode _reset c23 - cam_hs - - - gpio_94 hw_dbg0 - safe_mode c26 - cam_pclk - - - gpio_97 hw_dbg2 - safe_mode d26 - cam_strobe - - - gpio_126 hw_dbg11 - safe_mode c25 - cam_xclka - - - gpio_96 - - safe_mode e25 - cam_xclkb - - - gpio_111 - - safe_mode p25 - cam_d6 - - - gpio_105 - - safe_mode p26 - cam_d7 - - - gpio_106 - - safe_mode n25 - cam_d8 - - - gpio_107 - - safe_mode n26 - cam_d9 - - - gpio_108 - - safe_mode d23 - cam_vs - - - gpio_95 hw_dbg1 - safe_mode a23 - cam_wen - cam_shutter - gpio_167 hw_dbg10 - safe_mode f26 - dss_acbias - - - gpio_69 - - safe_mode g26 - dss_data6 - uart1_tx - gpio_76 hw_dbg14 - safe_mode h25 - dss_data7 - uart1_rx - gpio_77 hw_dbg15 - safe_mode h26 - dss_data8 - - - gpio_78 hw_dbg16 - safe_mode j26 - dss_data9 - - - gpio_79 hw_dbg17 - safe_mode terminal description 80 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom l25 - dss_data16 - - - gpio_86 - - safe_mode l26 - dss_data17 - - - gpio_87 - - safe_mode m24 - dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode m26 - dss_data19 - mcspi3_sim dss_data1 gpio_89 - - safe_mode o n24 - dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode k24 - dss_hsync - - - gpio_67 hw_dbg13 - safe_mode m25 - dss_vsync - - - gpio_68 - - safe_mode r8 - mcspi1_cs1 - - mmc3_cmd gpio_175 - - safe_mode t8 - mcspi1_cs3 - hsusb2_tll_ hsusb2_dat gpio_177 mm2_txdat - safe_mode data2 a2 v9 - mcspi2_cs1 gpt8_pwm_ hsusb2_tll_ hsusb2_dat gpio_182 mm2_txen_ - safe_mode evt data3 a3 n t19 - mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode ab2 - etk_clk mcbsp5_clk mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ hw_dbg0 x stp ab3 - etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ hw_dbg1 clk ac3 - etk_d0 mcspi3_sim mmc3_dat4 hsusb1_dat gpio_14 mm1_rxrcv hsusb1_tll_ hw_dbg2 o a0 data0 ad4 - etk_d1 mcspi3_so - hsusb1_dat gpio_15 mm1_txse0 hsusb1_tll_ hw_dbg3 mi a1 data1 ad3 - etk_d2 mcspi3_cs0 - hsusb1_dat gpio_16 mm1_txdat hsusb1_tll_ hw_dbg4 a2 data2 aa3 - etk_d3 mcspi3_clk mmc3_dat3 hsusb1_dat gpio_17 - hsusb1_tll_ hw_dbg5 a7 data7 y3 - etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_dat gpio_18 - hsusb1_tll_ hw_dbg6 a4 data4 ab1 - etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_dat gpio_19 - hsusb1_tll_ hw_dbg7 a5 data5 ae3 - etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_dat gpio_20 - hsusb1_tll_ hw_dbg8 a6 data6 ad2 - etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_dat gpio_21 mm1_txen_ hsusb1_tll_ hw_dbg9 a3 n data3 aa4 - etk_d8 sys_drm_m mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ hw_dbg10 secure dir v2 - etk_d9 sys_secure mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ hw_dbg11 _indicator nxt ae4 - etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ hw_dbg12 clk af6 - etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ hw_dbg13 stp ae6 - etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ hw_dbg14 dir af7 - etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ hw_dbg15 nxt af9 - etk_d14 - - hsusb2_dat gpio_28 mm2_rxrcv hsusb2_tll_ hw_dbg16 a0 data0 ae9 - etk_d15 - - hsusb2_dat gpio_29 mm2_txse0 hsusb2_tll_ hw_dbg17 a1 data1 y15 - jtag_emu0 - - - gpio_11 - - safe_mode y14 - jtag_emu1 - - - gpio_31 - - safe_mode submit documentation feedback terminal description 81 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-5. multiplexing characteristics (cbc pkg.) (continued) ball ball top mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom u3 - mcbsp3_clk uart2_tx - - gpio_142 hsusb3_tll_ - safe_mode x data6 n3 - mcbsp3_dr uart2_rts - - gpio_141 hsusb3_tll_ - safe_mode data5 p3 - mcbsp3_dx uart2_cts - - gpio_140 hsusb3_tll_ - safe_mode data4 w3 - mcbsp3_fsx uart2_rx - - gpio_143 hsusb3_tll_ - safe_mode data7 v3 - mcbsp4_clk - - - gpio_152 hsusb3_tll_ mm3_txse0 safe_mode x data1 u4 - mcbsp4_dr - - - gpio_153 hsusb3_tll_ mm3_rxrcv safe_mode data0 r3 - mcbsp4_dx - - - gpio_154 hsusb3_tll_ mm3_txdat safe_mode data2 t3 - mcbsp4_fsx - - - gpio_155 hsusb3_tll_ mm3_txen_ safe_mode data3 n m3 - mmc2_dat5 mmc2_dir_d cam_global mmc3_dat1 gpio_137 hsusb3_tll_ mm3_rxdp safe_mode at1 _reset stp l3 - mmc2_dat6 mmc2_dir_c cam_shutter mmc3_dat2 gpio_138 hsusb3_tll_ - safe_mode md dir k3 - mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 hsusb3_tll_ mm3_rxdm safe_mode nxt w2 - uart1_cts - - - gpio_150 hsusb3_tll_ - safe_mode clk 82 terminal description submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-6. multiplexing characteristics (cus pkg.) (1) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom d7 sdrc_d0 - - - - - - - c5 sdrc_d1 - - - - - - - c6 sdrc_d2 - - - - - - - b5 sdrc_d3 - - - - - - - d9 sdrc_d4 - - - - - - - d10 sdrc_d5 - - - - - - - c7 sdrc_d6 - - - - - - - b7 sdrc_d7 - - - - - - - b11 sdrc_d8 - - - - - - - c12 sdrc_d9 - - - - - - - b12 sdrc_d10 - - - - - - - d13 sdrc_d11 - - - - - - - c13 sdrc_d12 - - - - - - - b14 sdrc_d13 - - - - - - - a14 sdrc_d14 - - - - - - - b15 sdrc_d15 - - - - - - - c9 sdrc_d16 - - - - - - - e12 sdrc_d17 - - - - - - - b8 sdrc_d18 - - - - - - - b9 sdrc_d19 - - - - - - - c10 sdrc_d20 - - - - - - - b10 sdrc_d21 - - - - - - - d12 sdrc_d22 - - - - - - - e13 sdrc_d23 - - - - - - - e15 sdrc_d24 - - - - - - - d15 sdrc_d25 - - - - - - - c15 sdrc_d26 - - - - - - - b16 sdrc_d27 - - - - - - - c16 sdrc_d28 - - - - - - - d16 sdrc_d29 - - - - - - - b17 sdrc_d30 - - - - - - - b18 sdrc_d31 - - - - - - - c18 sdrc_ba0 - - - - - - - d18 sdrc_ba1 - - - - - - - a4 sdrc_a0 - - - - - - - b4 sdrc_a1 - - - - - - - d6 sdrc_a2 - - - - - - - b3 sdrc_a3 - - - - - - - b2 sdrc_a4 - - - - - - - c3 sdrc_a5 - - - - - - - e3 sdrc_a6 - - - - - - - f6 sdrc_a7 - - - - - - - e10 sdrc_a8 - - - - - - - e9 sdrc_a9 - - - - - - - e7 sdrc_a10 - - - - - - - (1) na in table stands for not applicable. submit documentation feedback terminal description 83 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom g6 sdrc_a11 - - - - - - - g7 sdrc_a12 - - - - - - - f7 sdrc_a13 - - - - - - - f9 sdrc_a14 - - - - - - - a19 sdrc_ncs0 - - - - - - - b19 sdrc_ncs1 - - - - - - - a10 sdrc_clk - - - - - - - a11 sdrc_nclk - - - - - - - b20 sdrc_cke0 - - - - - - safe_mode c20 sdrc_cke1 - - - - - - safe_mode d19 sdrc_nras - - - - - - - c19 sdrc_ncas - - - - - - - a20 sdrc_nwe - - - - - - - b6 sdrc_dm0 - - - - - - - b13 sdrc_dm1 - - - - - - - a7 sdrc_dm2 - - - - - - - a16 sdrc_dm3 - - - - - - - a5 sdrc_dqs0 - - - - - - - a13 sdrc_dqs1 - - - - - - - a8 sdrc_dqs2 - - - - - - - a17 sdrc_dqs3 - - - - - - - k4 gpmc_a1 - - - gpio_34 - - safe_mode k3 gpmc_a2 - - - gpio_35 - - safe_mode k2 gpmc_a3 - - - gpio_36 - - safe_mode j4 gpmc_a4 - - - gpio_37 - - safe_mode j3 gpmc_a5 - - - gpio_38 - - safe_mode j2 gpmc_a6 - - - gpio_39 - - safe_mode j1 gpmc_a7 - - - gpio_40 - - safe_mode h1 gpmc_a8 - - - gpio_41 - - safe_mode h2 gpmc_a9 sys_ - - gpio_42 - - safe_mode ndmareq2 g2 gpmc_a10 sys_ - - gpio_43 - - safe_mode ndmareq3 l2 gpmc_d0 - - - - - - - m1 gpmc_d1 - - - - - - - m2 gpmc_d2 - - - - - - - n2 gpmc_d3 - - - - - - - m3 gpmc_d4 - - - - - - - p1 gpmc_d5 - - - - - - - p2 gpmc_d6 - - - - - - - r1 gpmc_d7 - - - - - - - r2 gpmc_d8 - - - gpio_44 - - safe_mode t2 gpmc_d9 - - - gpio_45 - - safe_mode u1 gpmc_d10 - - - gpio_46 - - safe_mode r3 gpmc_d11 - - - gpio_47 - - safe_mode t3 gpmc_d12 - - - gpio_48 - - safe_mode u2 gpmc_d13 - - - gpio_49 - - safe_mode terminal description 84 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom v1 gpmc_d14 - - - gpio_50 - - safe_mode v2 gpmc_d15 - - - gpio_51 - - safe_mode e2 gpmc_ncs0 - - - - - - - d2 gpmc_ncs3 sys_ - - gpio_54 - - safe_mode ndmareq0 f4 gpmc_ncs4 sys_ mcbsp4_clkx gpt9_pwm_ gpio_55 - - safe_mode ndmareq1 evt g5 gpmc_ncs5 sys_ mcbsp4_dr gpt10_pwm_ gpio_56 - - safe_mode ndmareq2 evt f3 gpmc_ncs6 sys_ mcbsp4_dx gpt11_pwm_ gpio_57 - - safe_mode ndmareq3 evt g4 gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_ gpio_58 - - safe_mode evt w2 gpmc_clk - - - gpio_59 - - safe_mode f1 gpmc_nadv_a - - - - - - - le f2 gpmc_noe - - - - - - - g3 gpmc_nwe - - - - - - - k5 gpmc_nbe0_c - - - gpio_60 - - safe_mode le l1 gpmc_nbe1 - - - gpio_61 - - safe_mode e1 gpmc_nwp - - - gpio_62 - - safe_mode c1 gpmc_wait0 - - - - - - - c2 gpmc_wait3 sys_ - - gpio_65 - - safe_mode ndmareq1 g22 dss_pclk - - - gpio_66 - - safe_mode e22 dss_hsync - - - gpio_67 - - safe_mode f22 dss_vsync - - - gpio_68 - - safe_mode j21 dss_acbias - - - gpio_69 - - safe_mode ac19 dss_data0 - uart1_cts - gpio_70 - - safe_mode ab19 dss_data1 - uart1_rts - gpio_71 - - safe_mode ad20 dss_data2 - - - gpio_72 - - safe_mode ac20 dss_data3 - - - gpio_73 - - safe_mode ad21 dss_data4 - uart3_rx_irrx - gpio_74 - - safe_mode ac21 dss_data5 - uart3_tx_irtx - gpio_75 - - safe_mode d24 dss_data6 - uart1_tx - gpio_76 - - safe_mode e23 dss_data7 - uart1_rx - gpio_77 - - safe_mode e24 dss_data8 - - - gpio_78 - - safe_mode f23 dss_data9 - - - gpio_79 - - safe_mode ac22 dss_data10 - - - gpio_80 - - safe_mode ac23 dss_data11 - - - gpio_81 - - safe_mode ab22 dss_data12 - - - gpio_82 - - safe_mode y22 dss_data13 - - - gpio_83 - - safe_mode w22 dss_data14 - - - gpio_84 - - safe_mode v22 dss_data15 - - - gpio_85 - - safe_mode j22 dss_data16 - - - gpio_86 - - safe_mode g23 dss_data17 - - - gpio_87 - - safe_mode g24 dss_data18 - mcspi3_clk dss_data0 gpio_88 - - safe_mode h23 dss_data19 - mcspi3_simo dss_data1 gpio_89 - - safe_mode submit documentation feedback terminal description 85 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom d23 dss_data20 - mcspi3_somi dss_data2 gpio_90 - - safe_mode k22 dss_data21 - mcspi3_cs0 dss_data3 gpio_91 - - safe_mode v21 dss_data22 - mcspi3_cs1 dss_data4 gpio_92 - - safe_mode w21 dss_data23 - - dss_data5 gpio_93 - - safe_mode aa23 tv_out2 - - - - - - - ab24 tv_out1 - - - - - - - ab23 tv_vfb1 - - - - - - - y23 tv_vfb2 - - - - - - - y24 tv_vref - - - - - - - a22 cam_hs - - - gpio_94 - - safe_mode e18 cam_vs - - - gpio_95 - - safe_mode b22 cam_xclka - - - gpio_96 - - safe_mode j19 cam_pclk - - - gpio_97 - - safe_mode h24 cam_fld - cam_global_r - gpio_98 - - safe_mode eset ab18 cam_d0 - - - gpio_99 - - safe_mode ac18 cam_d1 - - - gpio_100 - - safe_mode g19 cam_d2 - - - gpio_101 - - safe_mode f19 cam_d3 - - - gpio_102 - - safe_mode g20 cam_d4 - - - gpio_103 - - safe_mode b21 cam_d5 - - - gpio_104 - - safe_mode l24 cam_d6 - - - gpio_105 - - safe_mode k24 cam_d7 - - - gpio_106 - - safe_mode j23 cam_d8 - - - gpio_107 - - safe_mode k23 cam_d9 - - - gpio_108 - - safe_mode f21 cam_d10 - - - gpio_109 - - safe_mode g21 cam_d11 - - - gpio_110 - - safe_mode c22 cam_xclkb - - - gpio_111 - - safe_mode f18 cam_wen - cam_shutter - gpio_167 - - safe_mode j20 cam_strobe - - - gpio_126 - - safe_mode v20 mcbsp2_fsx - - - gpio_116 - - safe_mode t21 mcbsp2_clkx - - - gpio_117 - - safe_mode v19 mcbsp2_dr - - - gpio_118 - - safe_mode r20 mcbsp2_dx - - - gpio_119 - - safe_mode m23 mmc1_clk - - - gpio_120 - - safe_mode l23 mmc1_cmd - - - gpio_121 - - safe_mode m22 mmc1_dat0 - - - gpio_122 - - safe_mode m21 mmc1_dat1 - - - gpio_123 - - safe_mode m20 mmc1_dat2 - - - gpio_124 - - safe_mode n23 mmc1_dat3 - - - gpio_125 - - safe_mode n22 mmc1_dat4 - - - gpio_126 - - safe_mode n21 mmc1_dat5 - - - gpio_127 - - safe_mode n20 mmc1_dat6 - - - gpio_128 - - safe_mode p24 mmc1_dat7 - - - gpio_129 - - safe_mode y1 mmc2_clk mcspi3_clk - - gpio_130 - - safe_mode ab5 mmc2_cmd mcspi3_simo - - gpio_131 - - safe_mode ab3 mmc2_dat0 mcspi3_somi - - gpio_132 - - safe_mode terminal description 86 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom y3 mmc2_dat1 - - - gpio_133 - - safe_mode w3 mmc2_dat2 mcspi3_cs1 - - gpio_134 - - safe_mode v3 mmc2_dat3 mcspi3_cs0 - - gpio_135 - - safe_mode ab2 mmc2_dat4 mmc2_dir_ - mmc3_dat0 gpio_136 - - safe_mode dat0 aa2 mmc2_dat5 mmc2_dir_ cam_global_r mmc3_dat1 gpio_137 - - safe_mode dat1 eset y2 mmc2_dat6 mmc2_dir_ cam_shutter mmc3_dat2 gpio_138 - - safe_mode cmd aa1 mmc2_dat7 mmc2_clkin - mmc3_dat3 gpio_139 - - safe_mode v6 mcbsp3_dx uart2_cts - - gpio_140 - - safe_mode v5 mcbsp3_dr uart2_rts - - gpio_141 - - safe_mode w4 mcbsp3_clkx uart2_tx - - gpio_142 - - safe_mode v4 mcbsp3_fsx uart2_rx - - gpio_143 - - safe_mode w7 uart1_tx - - - gpio_148 - - safe_mode w6 uart1_rts - - - gpio_149 - - safe_mode ac2 uart1_cts - - - gpio_150 - - safe_mode v7 uart1_rx - mcbsp1_clkr mcspi4_clk gpio_151 - - safe_mode w19 mcbsp1_clkr mcspi4_clk - - gpio_156 - - safe_mode ab20 mcbsp1_fsr - cam_global_r - gpio_157 - - safe_mode eset w18 mcbsp1_dx mcspi4_simo mcbsp3_dx - gpio_158 - - safe_mode y18 mcbsp1_dr mcspi4_somi mcbsp3_dr - gpio_159 - - safe_mode aa18 mcbsp_clks - cam_shutter - gpio_160 uart1_cts - safe_mode aa19 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx - gpio_161 - - safe_mode v18 mcbsp1_clkx - mcbsp3_clkx - gpio_162 - - safe_mode a23 uart3_cts_rctx - - - gpio_163 - - safe_mode b23 uart3_rts_sd - - - gpio_164 - - safe_mode b24 uart3_rx_irrx - - - gpio_165 - - safe_mode c23 uart3_tx_irtx - - - gpio_166 - - safe_mode r21 hsusb0_clk - - - gpio_120 - - safe_mode r23 hsusb0_stp - - - gpio_121 - - safe_mode p23 hsusb0_dir - - - gpio_122 - - safe_mode r22 hsusb0_nxt - - - gpio_124 - - safe_mode t24 hsusb0_ - uart3_tx_irtx - gpio_125 - - safe_mode data0 t23 hsusb0_ - uart3_rx_irrx - gpio_130 - - safe_mode data1 u24 hsusb0_ - uart3_rts_sd - gpio_131 - - safe_mode data2 u23 hsusb0_ - uart3_cts_ - gpio_169 - - safe_mode data3 rctx w24 hsusb0_ - - - gpio_188 - - safe_mode data4 v23 hsusb0_ - - - gpio_189 - - safe_mode data5 w23 hsusb0_ - - - gpio_190 - - safe_mode data6 t22 hsusb0_ - - - gpio_191 - - safe_mode data7 submit documentation feedback terminal description 87 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom k20 i2c1_scl - - - - - - - k21 i2c1_sda - - - - - - - ac15 i2c2_scl - - - gpio_168 - - safe_mode ac14 i2c2_sda - - - gpio_183 - - safe_mode ac13 i2c3_scl - - - gpio_184 - - safe_mode ac12 i2c3_sda - - - gpio_185 - - safe_mode y16 i2c4_scl sys_ - - - - - safe_mode nvmode1 y15 i2c4_sda sys_ - - - - - safe_mode nvmode2 a24 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 - - safe_mode t5 mcspi1_clk mmc2_dat4 - - gpio_171 - - safe_mode r4 mcspi1_simo mmc2_dat5 - - gpio_172 - - safe_mode t4 mcspi1_somi mmc2_dat6 - - gpio_173 - - safe_mode t6 mcspi1_cs0 mmc2_dat7 - - gpio_174 - - safe_mode r5 mcspi1_cs3 - hsusb2_tll_ hsusb2_ gpio_177 mm2_txdat - safe_mode data2 data2 n5 mcspi2_clk - hsusb2_tll_ hsusb2_ gpio_178 - - safe_mode data7 data7 n4 mcspi2_simo gpt9_pwm_ hsusb2_tll_ hsusb2_ gpio_179 - - safe_mode evt data4 data4 n3 mcspi2_somi gpt10_pwm_ hsusb2_tll_ hsusb2_ gpio_180 - - safe_mode evt data5 data5 m5 mcspi2_cs0 gpt11_pwm_ hsusb2_tll_ hsusb2_ gpio_181 - - safe_mode evt data6 data6 m4 mcspi2_cs1 gpt8_pwm_ hsusb2_tll_ hsusb2_ gpio_182 mm2_txen_n - safe_mode evt data3 data3 aa16 sys_32k - - - - - - - ad15 sys_xtalin - - - - - - - ad14 sys_xtalout - - - - - - - y13 sys_clkreq - - - gpio_1 - - safe_mode w16 sys_nirq - - - gpio_0 - - safe_mode aa10 sys_nrespwro - - - - - - - n y10 sys_nreswar - - - gpio_30 - - safe_mode m ab12 sys_boot0 - - - gpio_2 - - safe_mode ac16 sys_boot1 - - - gpio_3 - - safe_mode ad17 sys_boot2 - - - gpio_4 - - safe_mode ad18 sys_boot3 - - - gpio_5 - - safe_mode ac17 sys_boot4 mmc2_dir_ - - gpio_6 - - safe_mode dat2 ab16 sys_boot5 mmc2_dir_ - - gpio_7 - - safe_mode dat3 aa15 sys_boot6 - - - gpio_8 - - safe_mode ad23 sys_off_ - - - gpio_9 - - safe_mode mode y7 sys_clkout1 - - - gpio_10 - - safe_mode aa6 sys_clkout2 - - - gpio_186 - - safe_mode a1 sys_ipmcsws - - - - - - - terminal description 88 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-6. multiplexing characteristics (cus pkg.) (continued) ball mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 bottom a2 sys_ - - - - - - - opmcsws ab7 jtag_ntrst - - - - - - - ab6 jtag_tck - - - - - - - aa7 jtag_rtck - - - - - - - aa9 jtag_tms_ - - - - - - - tmsc ab10 jtag_tdi - - - - - - - ab9 jtag_tdo - - - - - - - ac24 jtag_emu0 - - - gpio_11 - - safe_mode ad24 jtag_emu1 - - - gpio_31 - - safe_mode ac1 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hsusb1_tll_ - stp ad3 etk_ctl - mmc3_cmd hsusb1_clk gpio_13 - hsusb1_tll_ - clk ad6 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_ gpio_14 mm1_rxrcv hsusb1_tll_ - data0 data0 ac6 etk_d1 mcspi3_somi - hsusb1_ gpio_15 mm1_txse0 hsusb1_tll_ - data1 data1 ac7 etk_d2 mcspi3_cs0 - hsusb1_ gpio_16 mm1_txdat hsusb1_tll_ - data2 data2 ad8 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ gpio_17 - hsusb1_tll_ - data7 data7 ac5 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ gpio_18 - hsusb1_tll_ - data4 data4 ad2 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ gpio_19 - hsusb1_tll_ - data5 data5 ac8 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ gpio_20 - hsusb1_tll_ - data6 data6 ad9 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ gpio_21 mm1_txen_n hsusb1_tll_ - data3 data3 ac4 etk_d8 sys_drm_ mmc3_dat6 hsusb1_dir gpio_22 - hsusb1_tll_ - msecure dir ad5 etk_d9 sys_secure_ mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hsusb1_tll_ - indicator nxt ac3 etk_d10 - uart1_rx hsusb2_clk gpio_24 - hsusb2_tll_ - clk ac9 etk_d11 - - hsusb2_stp gpio_25 mm2_rxdp hsusb2_tll_ - stp ac10 etk_d12 - - hsusb2_dir gpio_26 - hsusb2_tll_ - dir ad11 etk_d13 - - hsusb2_nxt gpio_27 mm2_rxdm hsusb2_tll_ - nxt ac11 etk_d14 - - hsusb2_ gpio_28 mm2_rxrcv hsusb2_tll_ - data0 data0 ad12 etk_d15 - - hsusb2_ gpio_29 mm2_txse0 hsusb2_tll_ - data1 data1 submit documentation feedback terminal description 89 product preview
2.4 signal description 2.4.1 external memory interfaces omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com many signals are available on multiple pins according to the software configuration of the pin multiplexing options. 1. signal name: the signal name 2. description: description of the signal 3. type: type = ball type for this specific function: ? i = input ? o = output ? z = high-impedance ? d = open drain ? ds = differential ? a = analog 4. ball bottom: associated ball(s) bottom 5. ball top: associated ball(s) top 6. subsystem pin multiplexing: contains a list of the pin multiplexing options at the module/subsystem level. the pin function is selected at the module/system level. note: the subsystem multiplexing signals are not described in table 2-1 through table 2-6 . table 2-7. external memory interfaces ? gpmc signals description signal description [2] type ball ball ball ball top ball subsystem name [1] [3] botto top bottom (cbc pkg.) [5] botto pin m (cbb (cbb (cbc pkg.) [4] m multiplexin pkg.) [4] pkg.) [5] (cus g pkg.) [4] [6] gpmc_a1 general-purpose memory o n4 / k1 ac15 / j2 / aa2 - / u2 k4/ l2 gpmc_a17/ address bit 1 m2 gpmc_d0 gpmc_a2 general-purpose memory o m4 / l1 ab15 / h1 / aa1 - / u1 k3/ m1 gpmc_a18/ address bit 2 m1 gpmc_d1 gpmc_a3 general-purpose memory o l4 / l2 ac16 / h2 / ac2 - / v2 k2/ m2 gpmc_a19/ address bit 3 n2 gpmc_d2 gpmc_a4 general-purpose memory o k4 / p2 ab16 / g2 / ac1 - / v1 j4/ n2 gpmc_a20/ address bit 4 n1 gpmc_d3 gpmc_a5 general-purpose memory o t3 / t1 ac17 / f1 / ae5 - / aa3 j3/ m3 gpmc_a21/ address bit 5 r2 gpmc_d4 gpmc_a6 general-purpose memory o r3 / v1 ab17 / f2 / ad6 - / aa4 j2/ p1 gpmc_a22/ address bit 6 r1 gpmc_d5 gpmc_a7 general-purpose memory o n3 / v2 ac18 / e1 / ad5 - / y3 j1/ p2 gpmc_a23/ address bit 7 t2 gpmc_d6 gpmc_a8 general-purpose memory o m3 / w2 ab18 / e2 / ac5 - / y4 h1/ r1 gpmc_a24/ address bit 8 t1 gpmc_d7 gpmc_a9 general-purpose memory o l3 / h2 ac19 / d1 / v1 - / r1 h2/ r2 gpmc_a25/ address bit 9 ab3 gpmc_d8 gpmc_a10 general-purpose memory o k3 / k2 ab19 / d2 / y1 - / t1 g2/ t2 gpmc_a26/ address bit 10 ac3 gpmc_d9 gpmc_a11 general-purpose memory o p1 ab4 t1 n1 u1 gpmc_d10 address bit 11 gpmc_a12 general-purpose memory o r1 ac4 u2 p2 r3 gpmc_d11 address bit 12 gpmc_a13 general-purpose memory o r2 ab6 u1 p1 t3 gpmc_d12 address bit 13 gpmc_a14 general-purpose memory o t2 ac6 p1 m1 u2 gpmc_d13 address bit 14 terminal description 90 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-7. external memory interfaces ? gpmc signals description (continued) signal description [2] type ball ball ball ball top ball subsystem name [1] [3] botto top bottom (cbc pkg.) [5] botto pin m (cbb (cbb (cbc pkg.) [4] m multiplexin pkg.) [4] pkg.) [5] (cus g pkg.) [4] [6] gpmc_a15 general-purpose memory o w1 ab7 l2 j2 v1 gpmc_d14 address bit 15 gpmc_a16 general-purpose memory o y1 ac7 m2 k2 v2 gpmc_d15 address bit 16 gpmc_a17 general-purpose memory o n4 ac15 j2 - k4 gpmc_a1 address bit 17 gpmc_a18 general-purpose memory o m4 ab15 h1 - k3 gpmc_a2 address bit 18 gpmc_a19 general-purpose memory o l4 ac16 h2 - k2 gpmc_a3 address bit 19 gpmc_a20 general-purpose memory o k4 ab16 g2 - j4 gpmc_a4 address bit 20 gpmc_a21 general-purpose memory o t3 ac17 f1 - j3 gpmc_a5 address bit 21 gpmc_a22 general-purpose memory o r3 ab17 f2 - j2 gpmc_a6 address bit 22 gpmc_a23 general-purpose memory o n3 ac18 e1 - j1 gpmc_a7 address bit 23 gpmc_a24 general-purpose memory o m3 ab18 e2 - h1 gpmc_a8 address bit 24 gpmc_a25 general-purpose memory o l3 ac19 d1 - h2 gpmc_a9 address bit 25 gpmc_a26 general-purpose memory o k3 ab19 d2 - g2 gpmc_a10 address bit 26 gpmc_d0 gpmc data bit 0 io k1 m2 aa1 u2 l2 gpmc_a1/ gpmc_d0 gpmc_d1 gpmc data bit 1 io l1 m1 aa1 u1 m1 gpmc_a2/ gpmc_d1 gpmc_d2 gpmc data bit 2 io l2 n2 ac2 v2 m2 gpmc_a3/ gpmc_d2 gpmc_d3 gpmc data bit 3 io p2 n1 ac1 v1 n2 gpmc_a4/ gpmc_d3 gpmc_d4 gpmc data bit 4 io t1 r2 ae5 aa3 m3 gpmc_a5/ gpmc_d4 gpmc_d5 gpmc data bit 5 io v1 r1 ad6 aa4 p1 gpmc_a6/ gpmc_d5 gpmc_d6 gpmc data bit 6 io v2 t2 ad5 y3 p2 gpmc_a7 /gpmc_d6 gpmc_d7 gpmc data bit 7 io w2 t1 ac5 y4 r1 gpmc_a8/ gpmc_d7 gpmc_d8 gpmc data bit 8 io h2 ab3 v1 r1 r2 gpmc_a9/ gpmc_d8 gpmc_d9 gpmc data bit 9 io k2 ac3 y1 t1 t2 gpmc_a10/ gpmc_d9 gpmc_d10 gpmc data bit 10 io p1 ab4 t1 n1 u1 gpmc_a11/ gpmc_d10 gpmc_d11 gpmc data bit 11 io r1 ac4 u2 p2 r3 gpmc_a12/ gpmc_d11 gpmc_d12 gpmc data bit 12 io r2 ab6 u1 p1 t3 gpmc_a13/ gpmc_d12 gpmc_d13 gpmc data bit 13 io t2 ac6 p1 m1 u2 gpmc_a14/ gpmc_d13 submit documentation feedback terminal description 91 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-7. external memory interfaces ? gpmc signals description (continued) signal description [2] type ball ball ball ball top ball subsystem name [1] [3] botto top bottom (cbc pkg.) [5] botto pin m (cbb (cbb (cbc pkg.) [4] m multiplexin pkg.) [4] pkg.) [5] (cus g pkg.) [4] [6] gpmc_d14 gpmc data bit 14 io w1 ab7 l2 j2 v1 gpmc_a15/ gpmc_d14 gpmc_d15 gpmc data bit 15 io y1 ac7 m2 k2 v2 gpmc_a16/ gpmc_d15 gpmc_ncs0 gpmc chip select bit 0 o g4 y2 ad8 aa8 e2 - gpmc_ncs1 gpmc chip select bit 1 o h3 y1 ad1 w1 na - gpmc_ncs2 gpmc chip select bit 2 o v8 na a3 - na - gpmc_ncs3 gpmc chip select bit 3 o u8 na b6 - d2 - gpmc_ncs4 gpmc chip select bit 4 o t8 na b4 - f4 - gpmc_ncs5 gpmc chip select bit 5 o r8 na c4 - g5 - gpmc_ncs6 gpmc chip select bit 6 o p8 na b5 - f3 - gpmc_ncs7 gpmc chip select bit 7 o n8 na c5 - g4 - gpmc_io_dir gpmc io direction control for o n8 na c5 - g4 - use with external transceivers gpmc_clk gpmc clock o t4 w2 n1 l1 w2 - gpmc_nadv_ address valid or address o f3 w1 ad10 aa9 f1 - ale latch enable gpmc_noe output enable o g2 v2 n2 l2 f2 - gpmc_nwe write enable o f4 v1 m1 k1 g3 - gpmc_nbe0_ lower byte enable. also used o g3 ac12 k2 - k5 - cle for command latch enable gpmc_nbe1 upper byte enable o u3 na j1 - l1 - gpmc_nwp flash write protect o h1 ab10 ac6 y5 e1 - gpmc_wait0 external indication of wait i m8 ab12 ac11 y10 c1 - gpmc_wait1 external indication of wait i l8 ac10 ac8 y8 na - gpmc_wait2 external indication of wait i k8 na b3 - na - gpmc_wait3 external indication of wait i j8 na c6 - c2 - table 2-8. external memory interfaces ? sdrc signals description signal description type (1) ball ball top ball bottom ball top ball bottom name bottom (cbb pkg.) (cbc pkg.) (cbc pkg.) (cus pkg.) (cbb pkg.) sdrc_d0 sdram data bit 0 io d6 j2 - d1 d7 sdrc_d1 sdram data bit 1 io c6 j1 - g1 c5 sdrc_d2 sdram data bit 2 io b6 g2 - g2 c6 sdrc_d3 sdram data bit 3 io c8 g1 - e1 b5 sdrc_d4 sdram data bit 4 io c9 f2 - d2 d9 sdrc_d5 sdram data bit 5 io a7 f1 - e2 d10 sdrc_d6 sdram data bit 6 io b9 d2 - b3 c7 sdrc_d7 sdram data bit 7 io a9 d1 - b4 b7 sdrc_d8 sdram data bit 8 io c14 b13 - a10 b11 sdrc_d9 sdram data bit 9 io b14 a13 - b11 c12 sdrc_d10 sdram data bit 10 io c15 b14 - a11 b12 sdrc_d11 sdram data bit 11 io b16 a14 - b12 d13 sdrc_d12 sdram data bit 12 io d17 b16 - a16 c13 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). terminal description 92 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-8. external memory interfaces ? sdrc signals description (continued) signal description type (1) ball ball top ball bottom ball top ball bottom name bottom (cbb pkg.) (cbc pkg.) (cbc pkg.) (cus pkg.) (cbb pkg.) sdrc_d13 sdram data bit 13 io c17 a16 - a17 b14 sdrc_d14 sdram data bit 14 io b17 b19 - b17 a14 sdrc_d15 sdram data bit 15 io d18 a19 - b18 b15 sdrc_d16 sdram data bit 16 io d11 b3 - b7 c9 sdrc_d17 sdram data bit 17 io b10 a3 - a5 e12 sdrc_d18 sdram data bit 18 io c11 b5 - b6 b8 sdrc_d19 sdram data bit 19 io d12 a5 - a6 b9 sdrc_d20 sdram data bit 20 io c12 b8 - a8 c10 sdrc_d21 sdram data bit 21 io a11 a8 -- b9 b10 sdrc_d22 sdram data bit 22 io b13 b9 - a9 d12 sdrc_d23 sdram data bit 23 io d14 a9 - b10 e13 sdrc_d24 sdram data bit 24 io c18 b21 - c21 e15 sdrc_d25 sdram data bit 25 io a19 a21 - d20 d15 sdrc_d26 sdram data bit 26 io b19 d22 - b19 c15 sdrc_d27 sdram data bit 27 io b20 d23 - c20 b16 sdrc_d28 sdram data bit 28 io d20 e22 - d21 c16 sdrc_d29 sdram data bit 29 io a21 e23 - e20 d16 sdrc_d30 sdram data bit 30 io b21 g22 - e21 b17 sdrc_d31 sdram data bit 31 io c21 g23 - g21 b18 sdrc_ba0 sdram bank select o h9 ab21 - aa18 c18 0 sdrc_ba1 sdram bank select o h10 ac21 - v20 d18 1 sdrc_a0 sdram address bit o a4 n22 - g20 a4 0 sdrc_a1 sdram address bit o b4 n23 - k20 b4 1 sdrc_a2 sdram address bit o b3 p22 - j20 d6 2 sdrc_a3 sdram address bit o c5 p23 - j21 b3 3 sdrc_a4 sdram address bit o c4 r22 - u21 b2 4 sdrc_a5 sdram address bit o d5 r23 - r20 c3 5 sdrc_a6 sdram address bit o c3 t22 - m21 e3 6 sdrc_a7 sdram address bit o c2 t23 - m20 f6 7 sdrc_a8 sdram address bit o c1 u22 - n20 e10 8 sdrc_a9 sdram address bit o d4 u23 - k21 e9 9 sdrc_a10 sdram address bit o d3 v22 - y16 e7 10 sdrc_a11 sdram address bit o d2 v23 - n21 g6 11 sdrc_a12 sdram address bit o d1 w22 - r21 g7 12 sdrc_a13 sdram address bit o e2 w23 - aa15 f7 13 submit documentation feedback terminal description 93 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-8. external memory interfaces ? sdrc signals description (continued) signal description type (1) ball ball top ball bottom ball top ball bottom name bottom (cbb pkg.) (cbc pkg.) (cbc pkg.) (cus pkg.) (cbb pkg.) sdrc_a14 sdram address bit o e1 y22 - y12 f9 14 sdrc_ncs0 chip select 0 o h11 m22 - t21 a19 sdrc_ncs1 chip select 1 o h12 m23 - t20 b19 sdrc_clk clock io a13 a11 - a12 a10 sdrc_nclk clock invert o a14 b11 - b13 a11 sdrc_cke0 clock enable 0 o h16 j22 - y15 b20 sdrc_cke1 clock enable 1 o h17 j23 - y13 c20 sdrc_nras sdram row o h14 l23 - v21 d19 access sdrc_ncas sdram column o h13 l22 - u20 c19 address strobe sdrc_nwe sdram write o h15 k23 - y18 a20 enable sdrc_dm0 data mask 0 o b7 c1 - h1 b6 sdrc_dm1 data mask 1 o a16 a17 - a14 b13 sdrc_dm2 data mask 2 o b11 a6 - a4 a7 sdrc_dm3 data mask 3 o c20 a20 - a18 a16 sdrc_dqs0 data strobe 0 io a6 c2 - c2 a5 sdrc_dqs1 data strobe 1 io a17 b17 - b15 a13 sdrc_dqs2 data strobe 2 io a10 b6 - b8 a8 sdrc_dqs3 data strobe 3 io a20 b20 - a19 a17 terminal description 94 submit documentation feedback product preview
2.4.2 video interfaces omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-9. video interfaces ? cam signals description signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) cam_hs camera horizontal io a24 c23 a22 synchronization cam_vs camera vertical synchronization io a23 d23 e18 cam_xclka camera clock output a o c25 c25 b22 cam_xclkb camera clock output b o b26 e25 c22 cam_d0 camera digital image data bit 0 i ag17 ae16 ab18 cam_d1 camera digital image data bit 1 i ah17 ae15 ac18 cam_d2 camera digital image data bit 2 i b24 a24 g19 cam_d3 camera digital image data bit 3 i c24 b24 f19 cam_d4 camera digital image data bit 4 i d24 d24 g20 cam_d5 camera digital image data bit 5 i a25 c24 b21 cam_d6 camera digital image data bit 6 i k28 p25 l24 cam_d7 camera digital image data bit 7 i l28 p26 k24 cam_d8 camera digital image data bit 8 i k27 n25 j23 cam_d9 camera digital image data bit 9 i l27 n26 k23 cam_d10 camera digital image data bit 10 i b25 d25 f21 cam_d11 camera digital image data bit 11 i c26 e26 g21 cam_fld camera field identification io c23 b23 h24 cam_pclk camera pixel clock i c27 c26 j19 cam_wen camera write enable i b23 a23 f18 cam_strobe flash strobe control signal o d25 d26 j20 cam_global_res global reset is used strobe io c23 / ah3 / aa21 v17 / b23 h24/ aa2/ ab20 et synchronization cam_shutter mechanical shutter control signal o b23 / af3 / t21 a23 / t19 f18/ y2/ aa18 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). table 2-10. video interfaces ? dss signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) dss_pclk lcd pixel clock o d28 g25 g22 dss_hsync lcd horizontal synchronization o d26 k24 e22 dss_vsync lcd vertical synchronization o d27 m25 f22 dss_acbias ac bias control (stn) or pixel data enable (tft) o e27 f26 j21 output dss_data0 lcd pixel data bit 0 io ag22 / h26 ae21 / m24 ac19 dss_data1 lcd pixel data bit 1 io ah22 / h25 ae22 / m26 ab19 dss_data2 lcd pixel data bit 2 io ag23 / e28 ae23 / f25 ad20 dss_data3 lcd pixel data bit 3 io ah23 / j26 ae24 / n24 ac20 dss_data4 lcd pixel data bit 4 io ag24 / ac27 ad23 / ac25 ad21 dss_data5 lcd pixel data bit 5 io ah24 / ac28 ad24/ ab25 ac21 dss_data6 lcd pixel data bit 6 io e26 g26 d24 dss_data7 lcd pixel data bit 7 io f28 h25 e23 dss_data8 lcd pixel data bit 8 io f27 h26 e24 dss_data9 lcd pixel data bit 9 io g26 j26 f23 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). submit documentation feedback terminal description 95 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-10. video interfaces ? dss signals description (continued) signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) dss_data10 lcd pixel data bit 10 io ad28 ac26 ac22 dss_data11 lcd pixel data bit 11 io ad27 ad26 ac23 dss_data12 lcd pixel data bit 12 io ab28 aa25 ab22 dss_data13 lcd pixel data bit 13 io ab27 y25 y22 dss_data14 lcd pixel data bit 14 io aa28 aa26 w22 dss_data15 lcd pixel data bit 15 io aa27 ab26 v22 dss_data16 lcd pixel data bit 16 io g25 l25 j22 dss_data17 lcd pixel data bit 17 io h27 l26 g23 dss_data18 lcd pixel data bit 18 io h26 m24 g24 dss_data19 lcd pixel data bit 19 io h25 m26 h23 dss_data20 lcd pixel data bit 20 o e28 f25 d23 dss_data21 lcd pixel data bit 21 o j26 n24 k22 dss_data22 lcd pixel data bit 22 o ac27 ac25 v21 dss_data23 lcd pixel data bit 23 o ac28 ab25 w21 table 2-11. video interfaces ? rfbi signals description signal description type (1) ball bottom ball bottom ball bottom subsystem pin name (cbb pkg.) (cbc pkg.) (cus pkg.) multiplexing (2) rfbi_a0 rfbi command/data control o e27 f26 j21 dss_acbias rfbi_cs0 1st lcd chip select o d26 k24 e22 dss_hsync rfbi_da0 rfbi data bus 0 io ag22 ae21 ac19 dss_data0 rfbi_da1 rfbi data bus 1 io ah22 ae22 ab19 dss_data1 rfbi_da2 rfbi data bus 2 io ag23 ae23 ad20 dss_data2 rfbi_da3 rfbi data bus 3 io ah23 ae24 ac20 dss_data3 rfbi_da4 rfbi data bus 4 io ag24 ad23 ad21 dss_data4 rfbi_da5 rfbi data bus 5 io ah24 ad24 ac21 dss_data5 rfbi_da6 rfbi data bus 6 io e26 g26 d24 dss_data6 rfbi_da7 rfbi data bus 7 io f28 h25 e23 dss_data7 rfbi_da8 rfbi data bus 8 io f27 h26 e24 dss_data8 rfbi_da9 rfbi data bus 9 io g26 j26 f23 dss_data9 rfbi_da10 rfbi data bus 10 io ad28 ac26 ac22 dss_data10 rfbi_da11 rfbi data bus 11 io ad27 ad26 ac23 dss_data11 rfbi_da12 rfbi data bus 12 io ab28 aa25 ab22 dss_data12 rfbi_da13 rfbi data bus 13 io ab27 y25 y22 dss_data13 rfbi_da14 rfbi data bus 14 io aa28 aa26 w22 dss_data14 rfbi_da15 rfbi data bus 15 io aa27 ab26 v22 dss_data15 rfbi_rd read enable for rfbi o d28 g25 g22 dss_pclk rfbi_wr write enable for rfbi o d27 m25 f22 dss_vsync rfbi_te_vsyn tearing effect removal and vsync i g25 l25 j22 dss_data16 c0 input from 1st lcd rfbi_hsync0 hsync for 1st lcd i h27 l26 g23 dss_data17 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). (2) the subsystem pin multiplexing options are not described in table 2-1 and table 2-4 terminal description 96 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-12. video interfaces ? tv signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) tv_out1 tv analog output composite: o y28 w26 ab24 tv_out1 tv_out2 tv analog output s-video: tv_out2 o w28 v26 aa23 tv_vfb1 tv_vfb1: feedback through external o y27 w25 ab23 resistorto composite tv_vfb2 tv_vfb2: feedback through external o w27 u24 y23 resistorto s-video tv_vref external capacitor i w26 v23 y24 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). submit documentation feedback terminal description 97 product preview
2.4.3 serial communication interfaces omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-13. serial communication interfaces ? hdq/1-wire signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) hdq_sio bidirectional hdq 1-wire control and data iod j25 j23 a24 interface. output is open drain. (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). table 2-14. serial communication interfaces ? i 2 c signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) inter-integrated circuit interface (i2c1) i2c1_scl i 2 c master serial clock. output is iod k21 j25 k20 open drain. i2c1_sda i 2 c serial bidirectional data. output iod j21 j24 k21 is open drain. inter-integrated circuit interface (i2c3) i2c3_scl i 2 c master serial clock. output is iod af14 c2 ac13 open drain. i2c3_sda i 2 c serial bidirectional data. output iod ag14 c1 ac12 is open drain. i2c3_sccbe tbd o j25 j23 a24 inter-integrated circuit interface (i2c2) i2c2_scl i 2 c master serial clock. output is iod af15 ab4 ac15 open drain. i2c2_sda i 2 c serial bidirectional data. output iod ae15 ac4 ac14 is open drain. i2c2_sccbe serial camera control bus enable o j25 j23 a24 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). table 2-15. serial communication interfaces ? smartreflex signals description (1) signal description type (2) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) inter-integrated circuit interface (i2c4) i2c4_scl i 2 c master serial clock. output is iod ad26 ad15 y16 open drain. i2c4_sda i 2 c serial bidirectional data. output iod ae26 w16 y15 is open drain. (1) for more information on smartreflex voltage control, see the prcm chapter of the omap35x technical reference manual (trm) [literature number sprufa5 ]. (2) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog). table 2-16. serial communication interfaces ? mcbsp lp signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) multichannel serial (mcbsp lp 1) mcbsp1_dr received serial data i u21 t20 y18 mcbsp1_clkr receive clock io y8 / y21 u19 / h3 v7 / w19 mcbsp1_fsr receive frame synchronization io aa21 v17 ab20 mcbsp1_dx transmitted serial data io v21 u17 w18 mcbsp1_clkx transmit clock io w21 t17 v18 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) terminal description 98 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-16. serial communication interfaces ? mcbsp lp signals description (continued) signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) mcbsp1_fsx transmit frame synchronization io k26 p20 aa19 mcbsp_clks external clock input (shared by i t21 t19 aa18 mcbsp1, 2, 3, 4, and 5) multichannel serial (mcbsp lp 2) mcbsp2_dr received serial data i r21 t18 v19 mcbsp2_dx transmitted serial data io m21 r19 r20 mcbsp2_clkx combined serial clock io n21 r18 t21 mcbsp2_fsx combined frame synchronization io p21 u18 v20 multichannel serial (mcbsp lp 3) mcbsp3_dr received serial data i ae6 / ab25 / u21 t20 / aa24 v5 / y18 mcbsp3_dx transmitted serial data io af6 / ab26 / v21 u17 / y24 v6 / w18 mcbsp3_clkx combined serial clock io af5 / aa25 / w21 t17 / ad22 w4 / v18 mcbsp3_fsx combined frame synchronization io ae5 / ad25 / k26 p20 / ad21 v4 / aa19 multichannel serial (mcbsp lp 4) mcbsp4_dr received serial data i r8 / ad1 c4 g5 mcbsp4_dx transmitted serial data io p8 / ad2 b5 f3 mcbsp4_clkx combined serial clock io t8 / ae1 b4 f4 mcbsp4_fsx combined frame synchronization io n8 / ac1 c5 g4 multichannel serial (mcbsp lp 5) mcbsp5_dr received serial data i ae11 y3 ac5 mcbsp5_dx transmitted serial data io af13 ae3 ac8 mcbsp5_clkx combined serial clock io af10 ab2 ac1 mcbsp5_fsx combined frame synchronization io ah9 ab1 ad2 table 2-17. serial communication interfaces ? mcspi signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) multichannel serial port interface (mcspi1) mcspi1_clk spi clock io ab3 p9 t5 mcspi1_simo slave data in, master data out io ab4 p8 r4 mcspi1_somi slave data out, master data in io aa4 p7 t4 mcspi1_cs0 spi enable 0, polarity io ac2 r7 t6 configured by software mcspi1_cs1 spi enable 1, polarity o ac3 r8 na configured by software mcspi1_cs2 spi enable 2, polarity o ab1 r9 na configured by software mcspi1_cs3 spi enable 3, polarity o ab2 t8 r5 configured by software multichannel serial port interface (mcspi2) mcspi2_clk spi clock io aa3 w7 n5 mcspi2_simo slave data in, master data out io y2 w8 n4 mcspi2_somi slave data out, master data in io y3 u8 n3 mcspi2_cs0 spi enable 0, polarity io y4 v8 m5 configured by software mcspi2_cs1 spi enable 1, polarity o v3 v9 m4 configured by software multichannel serial port interface (mcspi3) (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) submit documentation feedback terminal description 99 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-17. serial communication interfaces ? mcspi signals description (continued) signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) mcspi3_clk spi clock io h26 / ae2 / ae13 w10 / m24 / aa3 g24 / y1 / ad8 mcspi3_simo slave data in, master data out io h25 / ag5 / af11 r10 / m26 / ac3 h23 / ab5 / ad6 mcspi3_somi slave data out, master data in io e28 / ah5 / ag12 f25 / t10 / ad4 d23 / ab3 / ac6 mcspi3_cs0 spi enable 0, polarity io j26 / af4 / ah12 u9 / n24 / ad3 k22 / v3 / ac7 configured by software mcspi3_cs1 spi enable 1, polarity o ac27 / ag4 / ah14 ac25 / u10 / ad2 v21 / w3 / ad9 configured by software multichannel serial port interface (mcspi4) mcspi4_clk spi clock io y8 / y21 u19 / h3 v7 / w19 mcspi4_simo slave data in, master data out io v21 u17 w18 mcspi4_somi slave data out, master data in io u21 t20 y18 mcspi4_cs0 spi enable 0, polarity io k26 p20 aa19 configured by software table 2-18. serial communication interfaces ? uarts signals description signal description type (1) ball bottom ball bottom ball bottom name (cbb pkg.) (cbc pkg.) (cus pkg.) universal asynchronous receiver/transmitter (uart1) uart1_cts uart1 clear to send i ag22 / w8 / t21 ae21 / t19 ac19 / ac2 / aa18 uart1_rts uart1 request to send o ah22 / aa9 ae22 / r2 w6 / ab19 uart1_rx uart1 receive data i f28 / y8 / ae7 h3 / h25 / ae4 e23 / v7 / ac3 uart1_tx uart1 transmit data o e26 / aa8 l4 / g26 d24 / w7 universal asynchronous receiver/transmitter (uart2) uart2_cts uart2 clear to send i af6 / ab26 y24 v6 uart2_rts uart2 request to send o ae6 / ab25 aa24 v5 uart2_rx uart2 receive data i ae5 / ad25 ad21 v4 uart2_tx uart2 transmit data o af5 / aa25 ad22 w4 universal asynchronous receiver/transmitter (uart3) / irda uart3_cts_rct uart3 clear to send (input), io h18 / u26 w20 / f23 a23 / u23 x remote tx (output) uart3_rts_sd uart3 request to send, ir o h19 / u27 v18 / f24 b23 / u24 enable uart3_rx_irrx uart3 receive data, ir and i ag24 / h20 / u28 ad23 / y20 / h24 ad21 / b24 / t23 remote rx uart3_tx_irtx uart3 transmit data, ir tx o ah24 / h21 / t27 ad24/ v20 / g24 ac21 / c23 / t24 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) table 2-19. serial communication interfaces ? usb signals description signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) high-speed universal serial bus interface (hsusb0) hsusb0_clk dedicated for external transceiver 60-mhz clock input i t28 w19 r21 from phy hsusb0_stp dedicated for external transceiver stop signal o t25 u20 r23 hsusb0_dir dedicated for external transceiver data direction i r28 v19 p23 control from phy hsusb0_nxt dedicated for external transceiver next signal from i t26 w18 r22 phy (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) terminal description 100 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-19. serial communication interfaces ? usb signals description (continued) signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) hsusb0_data0 dedicated for external transceiver bidirectional data io t27 v20 t24 bus hsusb0_data1 dedicated for external transceiver bidirectional data io u28 y20 t23 bus hsusb0_data2 dedicated for external transceiver bidirectional data io u27 v18 u24 bus hsusb0_data3 dedicated for external transceiver bidirectional data io u26 w20 u23 bus hsusb0_data4 dedicated for external transceiver bidirectional data io u25 w17 w24 bus additional signals for 12-pin ulpi operation hsusb0_data5 dedicated for external transceiver bidirectional data io v28 y18 v23 bus additional signals for 12-pin ulpi operation hsusb0_data6 dedicated for external transceiver bidirectional data io v27 y19 w23 bus additional signals for 12-pin ulpi operation hsusb0_data7 dedicated for external transceiver bidirectional data io v26 y17 t22 bus additional signals for 12-pin ulpi operation mm_fsusb3 mm3_rxdm vminus receive data (not used in 3- or 4-pin io ae3 ae3 na configurations) mm3_rxdp vplus receive data (not used in 3- or 4-pin io ah3 m3 na configurations) mm3_rxrcv differential receiver signal input (not used in 3-pin io ad1 u4 (tbd) na mode) mm3_txse0 single-ended zero. used as vm in 4-pin vp_vm io ae1 v3 (tbd) na mode. mm3_txdat usb data. used as vp in 4-pin vp_vm mode. io ad2 t3 (tbd) na mm3_txen_n transmit enable io ac1 t3 (tbd) na mm_fsusb2 mm2_rxdm vminus receive data (not used in 3- or 4-pin io ah7 af7 ad11 configurations) mm2_rxdp vplus receive data (not used in 3- or 4-pin io af7 af6 ac9 configurations) mm2_rxrcv differential receiver signal input (not used in 3-pin io ag8 af9 ac11 mode) mm2_txse0 single-ended zero. used as vm in 4-pin vp_vm io ah8 ae9 ad12 mode. mm2_txdat usb data. used as vp in 4-pin vp_vm mode. io ab2 t8 r5 mm2_txen_n transmit enable io v3 v9 m4 mm_fsusb1 mm1_rxdm vminus receive data (not used in 3- or 4-pin io ag9 v2 ad5 configurations) mm1_rxdp vplus receive data (not used in 3- or 4-pin io af10 ab2 ac1 configurations) mm1_rxrcv differential receiver signal input (not used in 3-pin io af11 ac3 ad6 mode) mm1_txse0 single-ended zero. used as vm in 4-pin vp_vm io ag12 ad4 ac6 mode. mm1_txdat usb data. used as vp in 4-pin vp_vm mode. io ah12 ad3 ac7 mm1_txen_n transmit enable io ah14 ad2 ad9 hsusb3_tll hsusb3_tll_clk dedicated for external transceiver 60-mhz clock input o w8 w2 na from phy hsusb3_tll_stp dedicated for external transceiver stop signal i ah3 m3 na submit documentation feedback terminal description 101 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-19. serial communication interfaces ? usb signals description (continued) signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) hsusb3_tll_dir dedicated for external transceiver data direction o af3 l3 na control from phy hsusb3_tll_nxt dedicated for external transceiver next signal from o ae3 k3 na phy hsusb3_tll_data dedicated for external transceiver bidirectional data io ad1 u4 na 0 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io ae1 v3 na 1 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io ad2 r3 na 2 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io ac1 t3 na 3 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io af6 p3 na 4 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io ae6 n3 na 5 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io af5 u3 na 6 bus hsusb3_tll_data dedicated for external transceiver bidirectional data io ae5 w3 na 7 bus hsusb2 hsusb2_clk dedicated for external transceiver 60-mhz clock input o ae7 ae4 ac3 from phy hsusb2_stp dedicated for external transceiver stop signal o af7 af6 ac9 hsusb2_dir dedicated for external transceiver data direction i ag7 ae6 ac10 control from phy hsusb2_nxt dedicated for external transceiver next signal from i ah7 af7 ad11 phy hsusb2_data0 dedicated for external transceiver bidirectional data io ag8 af9 ac11 bus hsusb2_data1 dedicated for external transceiver bidirectional data io ah8 ae9 ad12 bus hsusb2_data2 dedicated for external transceiver bidirectional data io ab2 t8 r5 bus hsusb2_data3 dedicated for external transceiver bidirectional data io v3 v9 m4 bus hsusb2_data4 dedicated for external transceiver bidirectional data io y2 w8 n4 bus additional signals for 12-pin ulpi operation hsusb2_data5 dedicated for external transceiver bidirectional data io y3 u8 n3 bus additional signals for 12-pin ulpi operation hsusb2_data6 dedicated for external transceiver bidirectional data io y4 v8 m5 bus additional signals for 12-pin ulpi operation hsusb2_data7 dedicated for external transceiver bidirectional data io aa3 w7 n5 bus additional signals for 12-pin ulpi operation hsusb2_tll hsusb2_tll_clk dedicated for external transceiver 60-mhz clock input o ae7 ae4 ac3 from phy hsusb2_tll_stp dedicated for external transceiver stop signal i af7 af6 ac9 hsusb2_tll_dir dedicated for external transceiver data direction o ag7 ae6 ac10 control from phy hsusb2_tll_nxt dedicated for external transceiver next signal from o ah7 af7 ad11 phy hsusb2_tll_data dedicated for external transceiver bidirectional data io ag8 af9 ac11 0 bus terminal description 102 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-19. serial communication interfaces ? usb signals description (continued) signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) hsusb2_tll_data dedicated for external transceiver bidirectional data io ah8 ae9 ad12 1 bus hsusb2_tll_data dedicated for external transceiver bidirectional data io ab2 t8 r5 2 bus hsusb2_tll_data dedicated for external transceiver bidirectional data io v3 v9 m4 3 bus hsusb2_tll_data dedicated for external transceiver bidirectional data io y2 w8 n4 4 bus additional signals for 12-pin ulpi operation hsusb2_tll_data dedicated for external transceiver bidirectional data io y3 u8 n3 5 bus additional signals for 12-pin ulpi operation hsusb2_tll_data dedicated for external transceiver bidirectional data io y4 v8 m5 6 bus additional signals for 12-pin ulpi operation hsusb2_tll_data dedicated for external transceiver bidirectional data io aa3 w7 n5 7 bus additional signals for 12-pin ulpi operation hsusb1 hsusb1_clk dedicated for external transceiver 60-mhz clock input o ae10 ab3 ad3 from phy hsusb1_stp dedicated for external transceiver stop signal o af10 ab2 ac1 hsusb1_dir dedicated for external transceiver data direction i af9 aa4 ac4 control from phy hsusb1_nxt dedicated for external transceiver next signal from i ag9 v2 ad5 phy hsusb1_data0 dedicated for external transceiver bidirectional data io af11 ac3 ad6 bus hsusb1_data1 dedicated for external transceiver bidirectional data io ag12 ad4 ac6 bus hsusb1_data2 dedicated for external transceiver bidirectional data io ah12 ad3 ac7 bus hsusb1_data3 dedicated for external transceiver bidirectional data io ah14 ad2 ad9 bus hsusb1_data4 dedicated for external transceiver bidirectional data io ae11 y3 ac5 bus additional signals for 12-pin ulpi operation hsusb1_data5 dedicated for external transceiver bidirectional data io ah9 ab1 ad2 bus additional signals for 12-pin ulpi operation hsusb1_data6 dedicated for external transceiver bidirectional data io af13 ae3 ac8 bus additional signals for 12-pin ulpi operation hsusb1_data7 dedicated for external transceiver bidirectional data io ae13 aa7 ad8 bus additional signals for 12-pin ulpi operation hsusb1_tll hsusb1_tll_clk dedicated for external transceiver 60-mhz clock input o ae10 ab3 ad3 from phy hsusb1_tll_stp dedicated for external transceiver stop signal i af10 ab2 ac1 hsusb1_tll_dir dedicated for external transceiver data direction o af9 aa4 ac4 control from phy hsusb1_tll_nxt dedicated for external transceiver next signal from o ag9 v2 ad5 phy hsusb1_tll_data dedicated for external transceiver bidirectional data io af11 ac3 ad6 0 bus hsusb1_tll_data dedicated for external transceiver bidirectional data io ag12 ad4 ac6 1 bus hsusb1_tll_data dedicated for external transceiver bidirectional data io ah12 ad3 ac7 2 bus hsusb1_tll_data dedicated for external transceiver bidirectional data io ah14 ad2 ad9 3 bus submit documentation feedback terminal description 103 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-19. serial communication interfaces ? usb signals description (continued) signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) hsusb1_tll_data dedicated for external transceiver bidirectional data io ae11 y3 ac5 4 bus additional signals for 12-pin ulpi operation hsusb1_tll_data dedicated for external transceiver bidirectional data io ah9 ab1 ad2 5 bus additional signals for 12-pin ulpi operation hsusb1_tll_data dedicated for external transceiver bidirectional data io af13 ae3 ac8 6 bus additional signals for 12-pin ulpi operation hsusb1_tll_data dedicated for external transceiver bidirectional data io ae13 aa3 ad8 7 bus additional signals for 12-pin ulpi operation terminal description 104 submit documentation feedback product preview
2.4.4 removable media interfaces omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-20. removable media interfaces ? mmc/sdio signals description signal name description type ( ball bottom ball bottom ball bottom 1) (cbb pkg.) (cbc pkg.) (cus pkg.) multimedia memory card (mmc1) / secure digital io (sdio1) mmc1_clk mmc/sd output clock o n28 n19 m23 mmc1_cmd mmc/sd command signal io m27 l18 l23 mmc1_dat0 mmc/sd card data bit 0 / spi serial input io n27 m19 m22 mmc1_dat1 mmc/sd card data bit 1 io n26 m18 m21 mmc1_dat2 mmc/sd card data bit 2 io n25 k18 m20 mmc1_dat3 mmc/sd card data bit 3 io p28 n20 n23 mmc1_dat4 mmc/sd card data bit 4 io p27 m20 n22 mmc1_dat5 mmc/sd card data bit 5 io p26 p17 n21 mmc1_dat6 mmc/sd card data bit 6 io r27 p18 n20 mmc1_dat7 mmc/sd card data bit 7 io r25 p19 p24 multimedia memory card (mmc2) / secure digital io (sdio2) mmc2_clk mmc/sd output clock o ae2 w10 y1 mmc2_dir_dat0 direction control for dat0 signal case an external o ae4 v10 ab2 transceiver used mmc2_dir_dat1 direction control for dat1 and dat3 signals case o ah3 m3 (tbd) aa2 an external transceiver used mmc2_dir_dat2 direction control for dat2 signal case an external o af19 e4 ac17 transceiver used mmc2_dir_dat3 direction control for dat4, dat5, dat6, and o ae21 g3 ab16 dat7 signals case an external transceiver used mmc2_clkin mmc/sd input clock i ae3 k3 (tbd) aa1 mmc2_dat0 mmc/sd card data bit 0 io ah5 t10 ab3 mmc2_dat1 mmc/sd card data bit 1 io ah4 t9 y3 mmc2_dat2 mmc/sd card data bit 2 io ag4 u10 w3 mmc2_dat3 mmc/sd card data bit 3 io af4 u9 v3 mmc2_dat4 mmc/sd card data bit 4 io ae4 / ab3 p9 / v10 ab2 / t5 mmc2_dat5 mmc/sd card data bit 5 io ah3 / ab4 p8 aa2 / r4 mmc2_dat6 mmc/sd card data bit 6 io af3 / aa4 p7 y2 / t4 mmc2_dat7 mmc/sd card data bit 7 io ae3 / ac2 r7 aa1 / t6 mmc2_dir_cmd direction control for cmd signal case an external o af3 l3 (tbd) y2 transceiver is used mmc2_cmd mmc/sd command signal io ag5 r10 ab5 multimedia memory card (mmc3) / secure digital io (sdio3) mmc3_clk mmc/sd output clock o ab1 / af10 r9 / ab2 ac1 mmc3_cmd mmc/sd command signal io ac3 / ae10 r8 / ab3 ad3 mmc3_dat0 mmc/sd card data bit 0 / spi serial input io ae4 / ae11 v10 / y3 ab2 / ac5 mmc3_dat1 mmc/sd card data bit 1 io ah3 / ah9 ab1 aa2 / ad2 mmc3_dat2 mmc/sd card data bit 2 io af3 / af13 ae3 y2 / ac8 mmc3_dat3 mmc/sd card data bit 3 io ae3 / ae13 aa3 aa1 / ad8 mmc3_dat4 mmc/sd card data bit 4 io af11 ac3 ad6 mmc3_dat5 mmc/sd card data bit 5 io ag9 v2 ad5 mmc3_dat6 mmc/sd card data bit 6 io af9 aa4 ac4 mmc3_dat7 mmc/sd card data bit 7 io ah14 ad2 ad9 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) submit documentation feedback terminal description 105 product preview
2.4.5 test interfaces omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-21. test interfaces ? etk signals description signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) etk_ctl etk trace ctl o ae10 ab2 ad3 etk_clk etk trace clock o af10 ab3 ac1 etk_d0 etk data 0 o af11 ac3 ad6 etk_d1 etk data 1 o ag12 ad4 ac6 etk_d2 etk data 2 o ah12 ad3 ac7 etk_d3 etk data 3 o ae13 aa3 ad8 etk_d4 etk data 4 o ae11 y3 ac5 etk_d5 etk data 5 o ah9 ab1 ad2 etk_d6 etk data 6 o af13 ae3 ac8 etk_d7 etk data 7 o ah14 ad2 ad9 etk_d8 etk data 8 o af9 aa4 ac4 etk_d9 etk data 9 o ag9 v2 ad5 etk_d10 etk data 10 o ae7 ae4 ac3 etk_d11 etk data 11 o af7 af6 ac9 etk_d12 etk data 12 o ag7 ae6 ac10 etk_d13 etk data 13 o ah7 af7 ad11 etk_d14 etk data 14 o ag8 af9 ac11 etk_d15 etk data 15 o ah8 ae9 ad12 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) 106 terminal description submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-22. test interfaces ? jtag signals description signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) jtag_ntrst test reset i aa17 u15 ab7 jtag_tck test clock i aa13 v14 ab6 jtag_rtck arm clock o aa12 w13 aa7 emulation jtag_tms_tmsc test mode select io aa18 v15 aa9 jtag_tdi test data input i aa20 u16 ab10 jtag_tdo test data output o aa19 y13 ab9 jtag_emu0 test emulation 0 io aa11 y15 ac24 jtag_emu1 test emulation 1 io aa10 y14 ad24 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) table 2-23. test interfaces ? sdti signals description signal description type (1) ball bottom ball bottom ball bottom subsystem name (cbb pkg.) (cbc pkg.) (cus pkg.) signal multiplexing (2) sdti_clk serial clock dual edge o af7 / aa11 / af6 / y15 / af9 ac9 / ac24 / etk_d11 / jtag_emu0 / ag8 ac11 etk_d14 sdti_txd0 serial data out (system trace o ag7 / aa10 / ae6 / y14 / y15 ac10 / ad24 / etk_d12 / jtag_emu1 / messages) aa11 ac24 jtag_emu0 sdti_txd1 serial data out (system trace o ah7 / aa10 af7 / y14 ad11 / ad24 etk_d13 / jtag_emu1 messages) sdti_txd2 serial data out (system trace o ag8 af9 ac11 etk_d14 messages) sdti_txd3 serial data out (system trace o ah8 ae9 ad12 etk_d15 messages) (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) (2) the subsystem pin multiplexing options are not described in table 2-1 and table 2-4 table 2-24. test interfaces ? hwdbg signals description signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) hw_dbg0 debug signal 0 o a24 / af10 c23/ab2 ad3 hw_dbg1 debug signal 1 o a23 / ae10 d23/ab3 ac1 hw_dbg2 debug signal 2 o c27/ af11 c26/ac3 ad6 hw_dbg3 debug signal 3 o c23 / ag12 b23/ad4 ac6 hw_dbg4 debug signal 4 o b24 / ah12 a24/ad3 ac7 hw_dbg5 debug signal 5 o c24 / ae13 b24/aa3 ad8 hw_dbg6 debug signal 6 o d24 / ae11 d24/y3 ac5 hw_dbg7 debug signal 7 o a25 / ah9 c24/ab1 ad2 hw_dbg8 debug signal 8 o b25 / af13 d25/ae3 ac8 hw_dbg9 debug signal 9 o c26 / ah14 e26/ad2 ad9 hw_dbg10 debug signal 10 o b23 / af9 a23/aa4 ac4 hw_dbg11 debug signal 11 o d25 / ag9 d26/v2 ad5 hw_dbg12 debug signal 12 o d28 / ae7 g25/ae4 ac3 hw_dbg13 debug signal 13 o d26 / af7 k24/af6 ac9 hw_dbg14 debug signal 14 o e26 / ag7 g26/ae6 ac10 hw_dbg15 debug signal 15 o f28 / ah7 h25/af7 ad11 hw_dbg16 debug signal 16 o f27 / ag8 h26/af9 ac11 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) submit documentation feedback terminal description 107 product preview
2.4.6 miscellaneous omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-24. test interfaces ? hwdbg signals description (continued) signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) hw_dbg17 debug signal 17 o g26 / ah8 j26/ae9 ad12 table 2-25. miscellaneous ? gp timer signals description signal name description type (1) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpt8_pwm_evt pwm or event for io n8 / ad25 / v3 c5 / ad21/ v9 g4/ m4 gp timer 8 gpt9_pwm_evt pwm or event for io t8 / ab26 / y2 b4 / w8 / y24 f4 / n4 gp timer 9 gpt10_pwm_evt pwm or event for io r8 / ab25 / y3 c4 / u8 / aa24 g5 / n3 gp timer 10 gpt11_pwm_evt pwm or event for io p8 / aa25 / y4 b5 / v8 / ad22 f3 / m5 gp timer 11 (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) table 2-26. miscellaneous - reserved pins ball bottom ball top signal name description type (cbb pkg.) (cus pkg.) rsv01 reserved pin. leave unconnected na ah20 na terminal description 108 submit documentation feedback product preview
2.4.7 general-purpose ios omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-27. general-purpose ios signals description (1) signal name description type (2) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpio_0 general-purpose io 0 io af26 v16 w16 gpio_1 general-purpose io 1 io af25 w15 y13 gpio_2 general-purpose io 2 io ah26 f3 ab12 gpio_3 general-purpose io 3 io ag26 d3 ac16 gpio_4 general-purpose io 4 io ae14 c3 ad17 gpio_5 general-purpose io 5 io af18 e3 ad18 gpio_6 general-purpose io 6 io af19 e4 ac17 gpio_7 general-purpose io 7 io ae21 g3 ab16 gpio_8 general-purpose io 8 io af21 d4 aa15 gpio_9 general-purpose io 9 io af22 v12 ad23 gpio_10 general-purpose io 10 io ag25 ae14 y7 gpio_11 general-purpose io 11 io aa11 y15 ac24 gpio_12 general-purpose io 12 io af10 ab2 ac1 gpio_13 general-purpose io 13 io ae10 ab3 ad3 gpio_14 general-purpose io 14 io af11 ac3 ad6 gpio_15 general-purpose io 15 io ag12 ad4 ac6 gpio_16 general-purpose io 16 io ah12 ad3 ac7 gpio_17 general-purpose io 17 io ae13 aa3 ad8 gpio_18 general-purpose io 18 io ae11 y3 ac5 gpio_19 general-purpose io 19 io ah9 ab1 ad2 gpio_20 general-purpose io 20 io af13 ae3 ac8 gpio_21 general-purpose io 21 io ah14 aa2 ad9 gpio_22 general-purpose io 22 io af9 aa4 ac4 gpio_23 general-purpose io 23 io ag9 v2 ad5 gpio_24 general-purpose io 24 io ae7 ae4 ac3 gpio_25 general-purpose io 25 io af7 af6 ac9 gpio_26 general-purpose io 26 io ag7 ae6 ac10 gpio_27 general-purpose io 27 io ah7 af7 ad11 gpio_28 general-purpose io 28 io ag8 af9 ac11 gpio_29 general-purpose io 29 io ah8 ae9 ad12 gpio_30 general-purpose io 30 io af24 ad7 y10 gpio_31 general-purpose io 31 io aa10 y14 ad24 gpio_34 general-purpose io 34 io n4 j2 k4 gpio_35 general-purpose io 35 io m4 h1 k3 gpio_36 general-purpose io 36 io l4 h2 k2 gpio_37 general-purpose io 37 io k4 g2 j4 gpio_38 general-purpose io 38 io t3 f1 j3 gpio_39 general-purpose io 39 io r3 f2 j2 gpio_40 general-purpose io 40 io n3 e1 j1 gpio_41 general-purpose io 41 io m3 e2 h1 gpio_42 general-purpose io 42 io l3 d1 h2 gpio_43 general-purpose io 43 io k3 d2 g2 gpio_44 general-purpose io 44 io h2 v1 r2 (1) na in table stands for not applicable. (2) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) submit documentation feedback terminal description 109 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-27. general-purpose ios signals description (continued) signal name description type (2) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpio_45 general-purpose io 45 io k2 y1 t2 gpio_46 general-purpose io 46 io p1 t1 u1 gpio_47 general-purpose io 47 io r1 u2 r3 gpio_48 general-purpose io 48 io r2 u1 t3 gpio_49 general-purpose io 49 io t2 p1 u2 gpio_50 general-purpose io 50 io w1 l2 v1 gpio_51 general-purpose io 51 io y1 m2 v2 gpio_52 general-purpose io 52 io h3 ad1 na gpio_53 general-purpose io 53 io v8 a3 na gpio_54 general-purpose io 54 io u8 b6 d2 gpio_55 general-purpose io 55 io t8 b4 f4 gpio_56 general-purpose io 56 io r8 c4 g5 gpio_57 general-purpose io 57 io p8 b5 f3 gpio_58 general-purpose io 58 io n8 c5 g4 gpio_59 general-purpose io 59 io t4 n1 w2 gpio_60 general-purpose io 60 io g3 k2 k5 gpio_61 general-purpose io 61 io u3 j1 l1 gpio_62 general-purpose io 62 io h1 ac6 e1 gpio_63 general-purpose io 63 io l8 ac8 na gpio_64 general-purpose io 64 io k8 b3 na gpio_65 general-purpose io 65 io j8 c6 c2 gpio_66 general-purpose io 66 io d28 g25 g22 gpio_67 general-purpose io 67 io d26 k24 e22 gpio_68 general-purpose io 68 io d27 m25 f22 gpio_69 general-purpose io 69 io e27 f26 j21 gpio_70 general-purpose io 70 io ag22 ae21 ac19 gpio_71 general-purpose io 71 io ah22 ae22 ab19 gpio_72 general-purpose io 72 io ag23 ae23 ad20 gpio_73 general-purpose io 73 io ah23 ae24 ac20 gpio_74 general-purpose io 74 io ag24 ad23 ad21 gpio_75 general-purpose io 75 io ah24 ad24 ac21 gpio_76 general-purpose io 76 io e26 g26 d24 gpio_77 general-purpose io 77 io f28 h25 e23 gpio_78 general-purpose io 78 io f27 h26 e24 gpio_79 general-purpose io 79 io g26 j26 f23 gpio_80 general-purpose io 80 io ad28 ac26 ac22 gpio_81 general-purpose io 81 io ad27 ad26 ac23 gpio_82 general-purpose io 82 io ab28 aa25 ab22 gpio_83 general-purpose io 83 io ab27 y25 y22 gpio_84 general-purpose io 84 io aa28 aa26 w22 gpio_85 general-purpose io 85 io aa27 ab26 v22 gpio_86 general-purpose io 86 io g25 l25 j22 gpio_87 general-purpose io 87 io h27 l26 g23 gpio_88 general-purpose io 88 io h26 m24 g24 gpio_89 general-purpose io 89 io h25 m26 h23 gpio_90 general-purpose io 90 io e28 f25 d23 terminal description 110 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-27. general-purpose ios signals description (continued) signal name description type (2) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpio_91 general-purpose io 91 io j26 n24 k22 gpio_92 general-purpose io 92 io ac27 ac25 v21 gpio_93 general-purpose io 93 io ac28 ab25 w21 gpio_94 general-purpose io 94 io a24 c23 a22 gpio_95 general-purpose io 95 io a23 d23 e18 gpio_96 general-purpose io 96 io c25 c25 b22 gpio_97 general-purpose io 97 io c27 c26 j19 gpio_98 general-purpose io 98 io c23 b23 h24 gpio_99 general-purpose io 99 i ag17 ae16 ab18 gpio_100 general-purpose io 100 i ah17 ae15 ac18 gpio_101 general-purpose io 101 io b24 a24 g19 gpio_102 general-purpose io 102 io c24 b24 f19 gpio_103 general-purpose io 103 io d24 d24 g20 gpio_104 general-purpose io 104 io a25 c24 b21 gpio_105 general-purpose io 105 io k28 p25 l24 gpio_106 general-purpose io 106 io l28 p26 k24 gpio_107 general-purpose io 107 io k27 n25 j23 gpio_108 general-purpose io 108 io l27 n26 k23 gpio_109 general-purpose io 109 io b25 d25 f21 gpio_110 general-purpose io 110 io c26 e26 g21 gpio_111 general-purpose io 111 io b26 e25 c22 gpio_112 general-purpose io 112 i ag19 ad17 na gpio_113 general-purpose io 113 i ah19 ad16 na gpio_114 general-purpose io 114 i ag18 ae18 na gpio_115 general-purpose io 115 i ah18 ae17 na gpio_116 general-purpose io 116 io p21 u18 v20 gpio_117 general-purpose io 117 io n21 r18 t21 gpio_118 general-purpose io 118 io r21 t18 v19 gpio_119 general-purpose io 119 io m21 r19 r20 gpio_120 general-purpose io 120 io n28 / t28 w19 / n19 m23 / r21 gpio_121 general-purpose io 121 io m27 / t25 u20 / l18 l23 / r23 gpio_122 general-purpose io 122 io n27 / r28 v19 / m19 m22 / p23 gpio_123 general-purpose io 123 io n26 m18 m21 gpio_124 general-purpose io 124 io n25 / t26 w18 / k18 m20 gpio_125 general-purpose io 125 io p28 / t27 v20 / n20 n23 gpio_126 general-purpose io 126 io d25 / p27 m20 / d26 j20 / n22 gpio_127 general-purpose io 127 io p26 p17 n21 gpio_128 general-purpose io 128 io r27 p18 n20 gpio_129 general-purpose io 129 io r25 p19 p24 gpio_130 general-purpose io 130 io ae2 / u28 y20 / w10 y1 / t23 gpio_131 general-purpose io 131 io ag5 / u27 v18 / r10 ab5 / u24 gpio_132 general-purpose io 132 io ah5 t10 ab3 gpio_133 general-purpose io 133 io ah4 t9 y3 gpio_134 general-purpose io 134 io ag4 u10 w3 gpio_135 general-purpose io 135 io af4 u9 v3 gpio_136 general-purpose io 136 io ae4 v10 ab2 submit documentation feedback terminal description 111 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-27. general-purpose ios signals description (continued) signal name description type (2) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpio_137 general-purpose io 137 io ah3 - aa2 gpio_138 general-purpose io 138 io af3 - y2 gpio_139 general-purpose io 139 io ae3 - aa1 gpio_140 general-purpose io 140 io af6 - v6 gpio_141 general-purpose io 141 io ae6 - v5 gpio_142 general-purpose io 142 io af5 - w4 gpio_143 general-purpose io 143 io ae5 - v4 gpio_144 general-purpose io 144 io ab26 y24 na gpio_145 general-purpose io 145 io ab25 aa24 na gpio_146 general-purpose io 146 io aa25 ad22 na gpio_147 general-purpose io 147 io ad25 ad21 na gpio_148 general-purpose io 148 io aa8 l4 w7 gpio_149 general-purpose io 149 io aa9 r2 w6 gpio_150 general-purpose io 150 io w8 - ac2 gpio_151 general-purpose io 151 io y8 h3 v7 gpio_152 general-purpose io 152 io ae1 - na gpio_153 general-purpose io 153 io ad1 - na gpio_154 general-purpose io 154 io ad2 - na gpio_155 general-purpose io 155 io ac1 - na gpio_156 general-purpose io 156 io y21 u19 w19 gpio_157 general-purpose io 157 io aa21 v17 ab20 gpio_158 general-purpose io 158 io v21 u17 w18 gpio_159 general-purpose io 159 io u21 t20 y18 gpio_160 general-purpose io 160 io t21 t19 aa18 gpio_161 general-purpose io 161 io k26 p20 aa19 gpio_162 general-purpose io 162 io w21 t17 v18 gpio_163 general-purpose io 163 io h18 f23 a23 gpio_164 general-purpose io 164 io h19 f24 b23 gpio_165 general-purpose io 165 io h20 h24 b24 gpio_166 general-purpose io 166 io h21 g24 c23 gpio_167 general-purpose io 167 io b23 a23 f18 gpio_168 general-purpose io 168 io af15 c2 ac15 gpio_169 general-purpose io 169 io u26 w20 u23 gpio_170 general-purpose io 170 io j25 j23 a24 gpio_171 general-purpose io 171 io ab3 p9 t5 gpio_172 general-purpose io 172 io ab4 p8 r4 gpio_173 general-purpose io 173 io aa4 p7 t4 gpio_174 general-purpose io 174 io ac2 r7 t6 gpio_175 general-purpose io 175 io ac3 r8 na gpio_176 general-purpose io 176 io ab1 r9 na gpio_177 general-purpose io 177 io ab2 t8 r5 gpio_178 general-purpose io 178 io aa3 w7 n5 gpio_179 general-purpose io 179 io y2 w8 n4 gpio_180 general-purpose io 180 io y3 u8 n3 gpio_181 general-purpose io 181 io y4 v8 m5 gpio_182 general-purpose io 182 io v3 v9 m4 terminal description 112 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-27. general-purpose ios signals description (continued) signal name description type (2) ball bottom ball bottom ball bottom (cbb pkg.) (cbc pkg.) (cus pkg.) gpio_183 general-purpose io 183 io ae15 c1 ac14 gpio_184 general-purpose io 184 io af14 ab4 ac13 gpio_185 general-purpose io 185 io ag14 ac4 ac12 gpio_186 general-purpose io 186 io ae22 w11 ae6 gpio_188 general-purpose io 188 io u25 w17 w24 gpio_189 general-purpose io 189 io v28 y18 v23 gpio_190 general-purpose io 190 io v27 y19 w23 gpio_191 general-purpose io 191 io v26 y17 t22 submit documentation feedback terminal description 113 product preview
2.4.8 system and miscellaneous terminals omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-28. system and miscellaneous signals description signal description type ( ball ball top ball ball top ball name 1) bottom (cbb pkg.) bottom (cbc pkg.) bottom (cbb pkg.) (cbc pkg.) (cus pkg.) sys_32k 32-khz clock input i ae25 na ae20 - aa16 sys_xtalin main input clock. oscillator input or i ae17 na af19 - ad15 lvcmos at 19.2, 13, or 12 mhz. sys_xtalout output of oscillator o af17 na af20 - ad14 sys_altclk alternate clock source selectable for i j25 na j23 - a24 gptimers (maximum 54 mhz), usb (48 mhz), or ntsc/pal (54 mhz) sys_clkreq request from omap35 15/03 device for io af25 na w15 - y13 system clock (open source type) sys_clkout1 configurable output clock1 o ag25 na ae14 - y7 sys_clkout2 configurable output clock2 o ae22 na w11 - aa6 sys_boot0 boot configuration mode bit 0 i ah26 na f3 - ab12 sys_boot1 boot configuration mode bit 1 i ag26 na d3 - ac16 sys_boot2 boot configuration mode bit 2 i ae14 na c3 - ad17 sys_boot3 boot configuration mode bit 3 i af18 na e3 - ad18 sys_boot4 boot configuration mode bit 4 i af19 na e4 - ac17 sys_boot5 boot configuration mode bit 5 i ae21 na g3 - ab16 sys_boot6 boot configuration mode bit 6 i af21 na d4 - aa15 sys_nrespwro power on reset i ah25 na v13 - aa10 n sys_nreswar warm boot reset (open drain output) iod af24 na ad7 - y10 m sys_nirq external fiq input i af26 na v16 - w16 sys_nvmode1 indicates the voltage mode o ad26 na ad15 - y16 sys_nvmode2 indicates the voltage mode o ae26 na w16 - y15 sys_off_mode indicates the voltage mode o af22 na v12 - ad23 sys_ndmareq external dma request 0 (system i u8 na b6 - d2 0 expansion). level (active low) or edge (falling) selectable. sys_ndmareq external dma request 1 (system i t8 / j8 na b4 / c6 - f4 / c2 1 expansion). level (active low) or edge (falling) selectable. sys_ndmareq external dma request 2 (system i l3 / r8 na d1 / c4 - h2 / g5 2 expansion). level (active low) or edge (falling) selectable. sys_ndmareq external dma request 3 (system i k3 / p8 na d2 / b5 - g2 / f3 3 expansion). level (active low) or edge (falling) selectable. sys_secure_ msecure transactions indicator o ag9 na v2 - ad5 indicator sys_drm_ msecure output o af9 na aa4 - ac4 msecure sys_ipmcsws reserved ai b1 na b1 - a1 sys_opmcsws reserved ao a1 na a2 - a2 pop_int0_ft pop dedicated control signal o ag11 ab9 af10 y9 na pop_int1_ft pop dedicated control signal o ah11 ac9 ae2 w2 na pop_tq_temp pop dedicated control signal na ah16 ac14 af14 aa12 na _ sense_ft (1) type = ball type for this specific function (i = input, o = output, z = high-impedance, d = open drain, ds = differential, a = analog) terminal description 114 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-28. system and miscellaneous signals description (continued) signal description type ( ball ball top ball ball top ball name 1) bottom (cbb pkg.) bottom (cbc pkg.) bottom (cbb pkg.) (cbc pkg.) (cus pkg.) pop_reset_rp pop dedicated control signal na ag13 ab11 - aa5 na _ft submit documentation feedback terminal description 115 product preview
2.4.9 power supplies omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 2-29. power supplies signals description (1) signal name description ball bottom ball top ball bottom ball top ball bottom (cbb pkg.) (cbb pkg.) (cbc pkg.) (cbc pkg.) (cus pkg.) vdd_mpu arm power y9 / w9 / t9 / r9 na h7/ n7/ u7/ v7/ n8/ na w13/ w12/ v13/ domain / m9 / l9 / j9 / g9/ l9/ m9/ w9/ v12/ u13/ u12/ y10 / u10 / t10 / y9/ m10/ p10/ k11/ t8/ t7/ r8/ r7/ r10 / n10 / m10 u11/ v11/ y11/ r6/ n8/ n7/ n6/ / l10 / j10 / y11 g12/ d13/ u13 m12/ m8/ m7/ / w11 / k11 / j11 m6/ l12/ l11/ / w12 / k13 / j10/ j9/ h10/ h9/ y14 / k14 / j14 / g10/ g9/f10 y15 / w15 / j15 vdd_core core power ac4 / j4 / h4 / na m7/ t7/ y8/ g11/ na t20/ t19/ t18/ domain d8 / ae9 / d9 / y12/ d15/ m17/ t17/ r19/ r18/ d15 / y16 / ae18 g18/ h20/ r20/ r17/ m15/ m14/ / y18 / w18 / ac21 l15/ l14/ k19/ k18 / j18 / ae19 k18/ k17/ j18/ / y19 / u19 / t19 j17/ h13/ h12/ / n19 / m19 / j19 g13/ g12/ f13/ / y20 / w20 / f12 v20 / u20 / p20 / n20 / k20 / j20 / d22 / d23 / ae24 / m25 / l25 / e25 cap_vdd_wkup wakeup/emu/me aa15 na k14 na y12 mory domains, connect capacitor bg_testout used for band gap u4 na d6 na ad1 test vdds_dpll_dll dll io power k15 na k13 na g18 domain (1.8 v): internal connection to pll_vdds, power supply for 3pll (1.8 v) vpp efuse g1 na d5 na b1 programmation vdda_dac video dac power v25 na v25 na ab13 plane vssa_dac video dac ground y26 na v24 na ab15 plane vdds io power plane ad3 / ad4 / w4 / na g4/ m4/ t4/ y4/ l7/ - y9 / w10 / w9 / af8 / ae8 / af16 ac7/ d9/ ae10/ v10 / v9 / u10 / / ae16 / af23 / c11/ j15/ ac15/ n19 / n18 / n17 / ae23 / f25 / f26 a18/ j18/ ac18/ m19 / m18 / m17 / ag27 / ae27/ ad20/ e24/ l24/ / h8 ag20/ h28/ t24/ w24/ ac24 ag21/p25 vdds_mem memory io power u1 / j1 / f1 / j2 / ac5 / p1 / h1 / k8 / k7 / k6 / j8 plane f2 / r4 / b5 / a5 f23 / e1 / c23 / / j7 / j6 / h15 / / ah6 / b8 / a8 / a4 / a7 / a10 / g16 / g15 / f16 / b12 / a12 / d16 / a15 / a18 f15 / e16 c16 / b18 / a18 / b22 / a22 / g28 / c28 vdds_dpll_per peripheral dplls aa16 na u14 na u17 power rail vdds_wkup_bg for wakeup ldo aa14 na w14 na aa13 and vdda (2 ldos sram and bg) (1) na = not applicable. terminal description 116 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 2-29. power supplies signals description (continued) signal name description ball bottom ball top ball bottom ball top ball bottom (cbb pkg.) (cbb pkg.) (cbc pkg.) (cbc pkg.) (cus pkg.) vss ground ag2 / u2 / b2 / h2 / b18 / ac20 / g1/ k1/ r1/ w1/ c1/ f1/ h2/ m2/ r2/ w15/ v16/ v15/ ag3 / w3 / p3 / ab5 / ab14 / b2/ h4/ n4/ r4/ y6/aa7/ y11/ aa16/ u16/ u15/ u14/ j3 / e3 / a3 / p4 ab20 / p2 / f22 / w4/ ab5/ a6/ d7/ w20/p20/ l21/ h20/ u11/ u9/t16/ / e4 / ag6 / d7 / e2 / c22 / b4 / y7/ae7/ a8/ g8/ f20/ b14/a13/ a7 t15/ t14/ t13/ c7 / v9 / u9 / p9 b7 / b10 / b15 d10/ g10/ l10/ t12/ t11/ t10/ / n9 / k9 / w10 / n10/ y10/ ac10/ t9/ r15/ r14/ v10 / p10 / k10 / c12/ d12/a13/ d14/ r11/ r10/ p17/ d10 / c10 / af12 ad14/ k15/ y16/ p15/ p14/ / ae12 / y12 / l17/ n17/ r17/ p13/p12/ p11/ k12 / j12 / y13 / d18/ d20/g20/ e22/ p10/ p8/ n16/ w13 / j13 / d13 / ab22/ g23/ l23/ n15/ n14/ n13/ c13 / w14 / k16 t23/ w23/ af23/ n12/ n11/ n10/ / j16 / y17 / w17 b25/ k25/u25/ n9/ m16/ m13/ / k17 / j17 / w19 ad25 m11/ m10/ m9/ / v19 / r19 / p19 l17/ l13/ l10/ / l19 / k19 / d19 l8/ k15/ k14/ / c19 / af20 / k11/ k10/ j16/ ae20 / t20 / r20 j15/ j14/ j13/ / m20 / l20 / d21 j12/ j11/h16/ / c22 / ac25 / h14/ h11 y25 / w25 / ac26 / r26 / l26 / a26 / g27 / b27 / aa26/ m28/ ag16/ ah21 vdds_sram sram ldos w16 na u12 na aa12 vdds_mmc1 mmc io power k25 na n23 na n24 domain for cmd, clk, and dat(0..3) vdds_mmc1a power supply for p25 na p23 na h8 mmc dat [4..7] cap_vdd_sram_ sram ldo v4 na n9 na u8 mpu capacitance for vddram1 cap_vdd_sram_ sram ldo l21 na k20 na h17 core capacitance for vddram2 pop_ddr_vdd_ft poped sdram a15 / j28 / m1 / aa23 / y23 / k1 / l1/af13/af17/af18 j1/aa11/y14/aa17/ na power af28 / ae28 h23 / a12 /a20/u26/k26 b16/p21/h21 pop_flash_vpp_ poped flash vpp ah13 ac11 aa11 af13 na ft pop_flash_vdd_ poped flash n1 / aa1 / af1 / ac8 / ac13 / af16/af22/t2/y2/a aa14/aa19/n2/t2/y na ft power ah10 / ah15 aa1 / u1 / l1 f8/af5 7/aa6 pop_vss_ft poped devices b15 / j27 / m2 / ab8 / ab13 / af15/af21/af24 aa13/y17/y19 na ground m26 / n2 / aa2 / aa2 / aa22 / u2 af2 / af27 / / l2 / k2 / k22 / ag10 / ag15 h22 / b12 submit documentation feedback terminal description 117 product preview
3 electrical characteristics 3.1 power domains omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the omap35 15/03 device integrates enhanced features that dynamically adapt energy consumption according to application needs and performance requirements. the omap35 15/03 device includes an enhanced power-management scheme based on: nine independent functional voltage domains on chip partitioning multiple voltage domains voltage scaling support enhanced memory retention support optimized device off mode centralized management of power, reset, and clock the external power supplies of omap35 15/03 are: vdd_mpu for the arm vdd_core for macros vdds for io macros vdds_mem for memory macros vdds_sram for sram ldos vdds_dpll_dll for dll io vdds_dpll_per for peripheral dplls vdds_wkup_bg for wakeup ldo and vdda (2 ldos: sram and bandgap) vdda_dac for video dac vdds_mmc1 for mmc io vpp for efuse the supply voltages are detailed in table 3-3 . figure 3-1 illustrates the power domains: 118 electrical characteristics submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 3-1. omap3515/03 power domains this power domain segmentation switches off (or places in retention state) domains that are unused while keeping others active. this implementation is based on internal switches that independently control each power domain. a power domain regular logic is attached to one of the device v dd supplies through a primary domain switch. when the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of the domain. embedded switches are implemented for all power domains except the wake-up domain. this allows the domain to be powered off, if not being used, to give maximum power savings. for more information, see the prcm chapter of the omap35x technical reference manual (trm) [literature number sprufa5 ]. all domain output signals at the interface between power domains are connected through isolation latch cells. these cells ensure a proper electrical isolation between the domains and an appropriate interface state at the domain boundaries. submit documentation feedback electrical characteristics 119 product preview mpu vdd_mpu domain core periph1 vdd_core domain dpll_mpu ldo in 1.8 v out 1.2 v dual video dac sram2 array sram 2 ldo 0 v/1.0 v/1.2 v sram1 array sram 1 ldo 0 v/1.0 v/1.2 v mmc1 vpp dpll_core ldo in 1.8 v out 1.2 v dpll4 ldo in 1.8 v out 1.2 v ldo3 1.0 v/1.2 v vdds periph2 dpll5 ldo in 1.8 v out 1.2 v wkup emu bandgap bck mem vss dll/dcdl hsdivider ldo efuse hsdivider ldo cap_vdd_sram_mpucap_vdd_sram_core tv_ref (for capacitor) vssa_dac vdd_mpu vdds_dpll_dll vdds_wkup_bg cap_vdd_wkup vdds_memvdds_sram omap device vdd_core vdds_mmc1 vdds_dpll_per vdda_dac 030-003 vdds mem vdds
3.2 absolute maximum ratings omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the following table specifies the absolute maximum ratings over the operating junction temperature range of omap commercial and extended temperature devices. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. the omap35 15/03 device adheres to eia/jesd22?a114, electrostatic discharge (esd) sensitivity testing human body model (hbm). minimum pass level for hbm is 2 kv. table 3-1. absolute maximum ratings over operating junction temperature range parameter min max unit vdd_mpu supply voltage range for core macros ?0.5 1.6 v vdd_core vdds second supply voltage range for 1.8-v i/o macros ?0.5 2.25 v vdds_mem vdds_mmc1 second supply voltage range for 1.8-v ios ?0.5 2.45 v vdds_mmc1a second supply voltage range for 3.0-v ios ?0.5 3.50 vdds_dsi supply voltage for dsi ?0.5 (1) 2.10 (1) v vdds_sdi supply voltage for sdi vdds_csi2 supply voltage for csi2 vdds_csib supply voltage for csib vdds_dpll_dll supply voltage for dll dpll ?0.5 2.10 v vdds_dpll_per supply voltage for per dpll vdds_sram supply voltage for sram ldos ?0.5 2.25 v vdds_wkup_bg supply voltage for wakeup ldo and vdda (2 ldos sram and bg) v pad voltage range csib (balls k28, l28, k27, l27) ?0.5 (1) 2.10 (1) v at pad csi2 (balls ag17, ah17, ag19, ah19, ag18, ah18) dsi (balls ag22, ah22, ag23, ah23, ag24, ah24) sdi (balls ad28, ad27, ab28, ab27, aa28, aa27, ac27, ac28) mmc1, ms (balls n28, m27, n27, supply voltage range ?0.54 (2) 2.34 (2) n26, n25, p28) for 1.8-v ios mmc1, sim (balls p27, p26, r27, supply voltage range ?0.45 (3) 3.45 (3) r25) for 3.0-v ios i2c1, i2c2, i2c3, i2c4 (balls k21, j21, af15, ae15, af14, ?0.63 (2) 2.73 (2) ag14, ad26, ae26) crystal (xtalin/xtalout) (balls ae17, af17) ?0.5 2.71 other balls ?0.5 vddsx (4) + 0.5 vdda_dac supply voltage range for analog macros ?0.5 2.43 v v esd esd stress hbm (human body model) (6) 2000 v voltage (5) cdm (charged device model) (7) 500 i ioi current-pulse injection on each i/o pin (8) 200 ma i clamp clamp current for an input or output ?20 20 ma (1) to be confirmed. (2) for a maximum time of 30% time period. (3) for a maximum time of 15% time period. (4) ) depending on ball, vddsx can be vdds_mem or vdds. (5) electrostatic discharge (esd) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. (6) jedec jesd22?a114 d with the following exception-no connect pins are not stressed. 2000v human body model (hbm) (7) jedec jesd22?c101c with the following exception-split out pin groupings to eliminate cumulative stress effect (8) each device is tested with i/o pin injection of 200 ma with a stress voltage of 1.5 times maximum vdd at room temperature. 120 electrical characteristics submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 3-1. absolute maximum ratings over operating junction temperature range (continued) parameter min max unit t stg storage temperature range (9) ?65 150 c this section includes the maximum power consumption for each power domain (core, etc.). table 3-2 summarizes the power consumption at the ball level. (9) these temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist. submit documentation feedback electrical characteristics 121 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 3-2. estimated maximum power consumption at ball level parameter max max unit ( t = 90 c) ( t = 105 c) signal description vdd_mpu processors omap35 15/03 (smartreflex? enabled) 686 728 ma omap35 15/03 (smartreflex? 850 911 disabled) vdd_core core omap35 (smartreflex? enabled) ma omap35 (smartreflex? disabled) omap35 (smartreflex? enabled) omap35(smartreflex? disabled) omap35 15 (smartreflex? enabled) 433 490 omap35 15 (smartreflex? disabled) 509 599 omap35 03 (smartreflex? enabled) 328 382 omap35 03(smartreflex? disabled) 378 485 vdda_dac video dac 65 65 ma vdss_dpll_dll dll + dpll mpu, and core 25 25 ma vdds_dpll_per dpll peripheral 1 and peripheral 2 15 15 ma vdds_sram processors and core ldo (ldo1 and ldo2) 41 41 ma vdds_wkup_bg bandgap, wakeup + ldo, emu off 6 6 ma vdds_mem standard i/os (sdrc+gpmc) 37 37 ma vdds standard i/os (all excluding sdrc and gpmc) 63 63 ma vdds_mmc1 mmc i/o (1) 20 20 ma vdds_mmc1a power supply for mmc io [dat4 ? dat8] 2 2 ma vpp efuse 50 50 ma (1) mmc card and i/o card are not included. electrical characteristics 122 submit documentation feedback product preview
3.3 recommended operating conditions omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 all omap35 15/03 modules are used under the operating conditions contained in table 3-3 . note: to avoid significant device degradation for commercial temperature omap35 15/OMAP3503 devices (0 c t j 90 c), the device power-on hours (poh) must be limited to one of the following: 100k total poh when operating across all opps and keeping the time spent at opp5 to less than 23k poh. 50k total poh when operating exclusively at opp5. 44k total poh with no restrictions to the proportion of these poh at operating points opp1 - opp5. to avoid significant device degradation for industrial temperature omap35 15a/OMAP3503a devices (-40 c t j 105 c), the following restrictions apply: opp5 is not supported.* the total device poh must be limited to less than 50k.* *if an industrial temperature device is operated such that t j never exceeds 90c (-40 c t j 90 c) then the opp poh limits for commercial devices indicated above apply. note: logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. table 3-3. recommended operating conditions parameter description min nom max unit v dd1 (vdd_mpu), omap processor opp5: overdrive v dd1nom - tbd v dd1nom + v smartreflex core supply (0.04*v dd1nom ) (0.04*v dd1nom ) enabled opp4: mid-overdrive v dd1nom - tbd v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp3: nominal v dd1nom - tbd v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp2: low-power v dd1nom - tbd v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp1: ultra low-power v dd1nom - tbd v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) v dd2 (vdd_core) omap processor opp3: nominal v dd2nom - tbd v dd2nom + v smartreflex core logic supply (0.04*v dd2nom ) (0.04*v dd2nom ) enabled opp2: low-power v dd2nom - tbd v dd2nom + v (0.04*v dd2nom ) (0.04*v dd2nom ) opp1: ultra low-power v dd2nom - tbd v dd2nom + v (0.04*v dd2nom ) (0.04*v dd2nom ) v dd1 (vdd_mpu), omap processor opp5: overdrive v dd1nom - 1.35 v dd1nom + v smartreflex core supply (0.04*v dd1nom ) (0.04*v dd1nom ) disabled opp4: mid-overdrive v dd1nom - 1.27 v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp3: nominal v dd1nom - 1.20 v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp2: low-power v dd1nom - 1.00 v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) opp1: ultra low-power v dd1nom - 0.95 v dd1nom + v (0.04*v dd1nom ) (0.04*v dd1nom ) v dd2 (vdd_core) omap processor opp3: nominal v dd2nom - 1.15 v dd2nom + v smartreflex core logic supply (0.04*v dd2nom ) (0.04*v dd2nom ) disabled opp2: low-power v dd2nom - 1.00 v dd2nom + v (0.04*v dd2nom ) (0.04*v dd2nom ) opp1: ultra low-power v dd2nom - 0.95 v dd2nom + v (0.04*v dd2nom ) (0.04*v dd2nom ) submit documentation feedback electrical characteristics 123 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 3-3. recommended operating conditions (continued) parameter description min nom max unit vdds supply voltage for i/o macros 1.71 1.8 1.89 v vdds_mem supply voltage for memory i/o macros 1.71 1.8 1.89 v vdds_mmc1 supply voltage for mmc1 macro in 1.8-v mode 1.71 1.8 1.89 v supply voltage for mmc1 macro in 3-v mode 2.7 3 3.3 v vdds_mmc1a power supply for sim i/os 1.71 1.8 1.89 v vdds_wkup_bg wakeup ldo 1.71 1.8 1.89 v vdda_dac analog supply voltage for video dac 1.71 1.8 1.89 v vdds_sram sram ldos 1.71 1.8 1.89 v vdds_dpll_per peripherals dplls power supply 1.71 1.8 1.89 v vdds_dpll_dll supply voltage for dplls i/os 1.71 1.8 1.89 v vpp (1) efuse programming v vss ground 0 0 0 v vssa_dac dedicated ground for dac 0 0 0 v t j operating commercial temperature 0 ? 90 c junction extended temperature -40 ? 105 c temperature range (1) it is recommended not to connect this pin. it is just used for efuse programming on package unit. 124 electrical characteristics submit documentation feedback product preview
3.4 dc electrical characteristics omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 3-4 summarizes the dc electrical characteristics. table 3-4. dc electrical characteristics parameter min nom max unit lvcmos pin buffers - cbb: n28, m27, n27, n26, n25, p28,p27, p26, r27, r25/ cbc: n19, l18, m19, m18, k18, n20, m20, p17, p18, p19/ cus: m23, l23, m22, m21, m20, n23 v ih high-level input voltage vdds (1) = 1.8 v 0.65 vdds (1) vdds + 0.3 v vdds (1) = 3.0 v 0.625 vdds + 0.3 vdds (1) v il low-level input voltage vdds (1) = 1.8 v ?0.3 0.35 vdds v vdds (1) = 3.0 v ?0.3 0.25 vdds v oh high-level output voltage (2) vdds (1) = 1.8 v vdds (1) ? 0.2 v vdds (1) = 3.0 v 0.75 vdds (1) v ol low-level output voltage (2) vdds (1) = 1.8 v 0.2 v vdds (1) = 3.0 v 0.125 vdds (1) t t input transition time (rise time, t r or fall time, normal mode 10 ns t f evaluated between 10% and 90% at pad) high-speed 3 mode lvds/cmos pin buffers - cbb: ag19, ah19, ag18, ah18, ag17, ah17/ cbc: ae16, ae15, ad17, ae18, ad16, ae17/ cus: ab18, ac18 low-power receiver (lp-rx) v il low-level input threshold 500 mv v ih high-level input threshold 800 mv v hys input hysteresis 25 mv ultralow-power receiver (ulp-rx) v il-ulpm low-level input threshold, ulpm 300 mv v ih high-level input threshold 880 mv high-speed receiver (hs-rx) v idth differential input high threshold 70 mv v idtl differential input low threshold ?70 mv v idmax maximum differential input voltage 270 mv v ilhs single-ended input low voltage ?40 mv v ihhs single-ended input high voltage 460 mv v cmrxdc common-mode voltage 70 330 mv lvds/cmos pin buffers - cbb: k28, l28, k27, l27/ cbc: p25, p26, n25, n26 / cus: l24, k24, j23, k23 v cm input common mode voltage range 600 900 1200 mv vos receiver input dc offset ?20 20 mv vid receiver input differential amplitude 140 200 400 mv t t input transition time (rise time, t r or fall time, t f evaluated 267 533 ps between 10% and 90% at pad) lvds/cmos pin buffers - cbb: ag22, ah22, ag23, ah23, ag24, ah24/ cbc: ae21, ae22, ae23, ae24, ad23, ad24 / cus: ac19, ab19, ad20, ac20, ad21, ac21 high-speed transceiver (hs-tx) v ohhs hs output high voltage 360 mv |v od | hs transmit differential voltage 140 200 270 mv v cmtx hs transmit static common mode voltage 150 200 250 mv low-power transceiver (lp-tx) (1) this global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, i 2 c). (2) with 100 m a sink / source current at vddsxmin. submit documentation feedback electrical characteristics 125 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 3-4. dc electrical characteristics (continued) parameter min nom max unit v ol thevenin output low level ?50 50 mv v oh thevenin output high level 1.1 1.2 1.3 v low-power receiver (lp-rx) v il low-level input threshold 550 mv v ih high-level input threshold 880 mv v hyst input hysteresis 25 mv ultralow-power receiver (ulp-rx) v il-ulps low-level input threshold, ulpm 300 mv v ih high-level input threshold 880 mv sublvds/cmos pin buffers - cbb: aa27, aa28, ab27, ab28, ad27, ad28, ac28, ac27/ cbc: ac26, ad26, aa25, y25, aa26, ab26, ac25, ab25/ cus: v22, w22, y22, ab22, ac23, ac22, w21, v21 vod differential voltage range @ r l = 100 w 100 150 200 mv vocm common mode voltage range 0.8 0.9 1 v t t input transition time (vod rise time, t r or vod fall time, t f 200 500 ps evaluated between 20% and 80% at pad) standard lvcmos pin buffers v ih (3) high-level input voltage (standard lvcmos) 0.65 vdds vdds + 0.3 v v il (3) low-level input voltage (standard lvcmos) - 0.3 0.35 vdds v v hys hysteresis voltage at an input (4) 0.1 v v oh high-level output voltage, driver enabled, i o = i oh or vdds ? 0.45 v pullup or pulldown disabled i o = ?2 ma i o = i oh < |?2| vdds ? 0.40 ma v ol low-level output voltage with , driver enabled, i o = i ol or 0.45 v pullup or pulldown disabled i o = 2 ma i o = i ol < 2 ma 0.40 t t input transition time (rise time, t r or fall time, t f evaluated 0 10 (1) ns between 10% and 90% at pad) i i input current with v i = v i max ?1 1 m a i oz off-state output current for output in high impedance with driver ?20 20 m a only, driver disabled off-state output current for output in high impedance with ?100 driver/receiver/pullup only, driver disabled, pullup not inhibited off-state output current for output in high impedance with 100 driver/receiver/pulldown only, driver disabled, pulldown not inhibited i z total leakage current through the pad connection of a ? 20 20 m a driver/receiver combination that may include a pullup or pulldown. the driver output is disabled and the pullup or pulldown is inhibited. lvcmos open-drain pin buffers dedicated to i2c ios - cbb: k21, j21, af14, ag14, af15, ae15, ad26, ae26/ cbc: j25, j24, c2, c1, ab4, ac4, ad15, w16, a21, c21/ cus: k20, k21, ac13, ac12, ac15, ac14, y16, y15 v ih high level input voltage 0.7 x vdds vdds + 0.5 v v il low level input voltage - 0.5 0.3 x vdds v v ol low-level output voltage open-drain at 3-ma sink current 0 0.2 x vdds v i i input current at each i/o pin with an input voltage between 0.1 x - 10 10 m a vdds to 0.9 x vdds c i capacitance for each i/o pin 10 pf (3) v ih /v il (standard lvcmos) parameters are applicable for sys_altclk input clocks. (4) v hys is the magnitude of the difference between the positive-going threshold voltage v t+ and the negative-going voltage v t- . electrical characteristics 126 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 3-4. dc electrical characteristics (continued) parameter min nom max unit t of output fall time from v ihmin to v ilmax with a fast mode 20 + 0.1c b 250 ns bus capacitance c b from 10 pf to 400 pf standard mode 250 output fall time with a capacitive load from 10 high-speed mode 10 40 pf to 100 pf at 3-ma sink current output fall time with a capacitive load of 400 20 80 pf at 3-ma sink current output fall time with a capacitive load of 40 20 pf (for cbus compatibility) lvcmos open-drain pin buffers dedicated in gpio mode - cbb: af15, ae15, af14, ag14, ad26, ae26 / cbc: c2, c1, ab4, ac4, ad15, w16, a21, c21/ cus: ac15, ac14, ac13, ac12, y16, y15 v ih high-level input voltage 0.7 x vdds vdds + 0.5 v v il low-level input voltage - 0.5 0.3 x vdds v v oh high-level output voltage at 4-ma sink current vdds - 0.45 v v ol low-level output voltage at 4-ma sink current 0.45 v submit documentation feedback electrical characteristics 127 product preview
3.5 core voltage decoupling omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com for module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. a decoupling capacitor is most effective when it is close to the device because this minimizes the inductance of the circuit board wiring and interconnects. table 3-5 summarizes the power supplies decoupling characteristics. table 3-5. core voltage decoupling characteristics parameter min typ max unit cvdd_mpu (1) 50 100 120 nf cvdd_core (1) 50 100 120 nf cvdds_sram 100 nf ccap_vdd_sram_mpu 0.7 1.0 1.3 m f ccap_vdd_sram_core 0.7 1.0 1.3 m f ccap_vdd_wkup 0.7 1.0 1.3 m f cvdds_wkup_bg 100 nf cvdds_dpll_dll 100 nf cvdds_dpll_per 100 nf cvdda_dac 100 nf cvdds_mmc1 100 nf cvdds_mmca 100 nf (1) 1 capacitor per 2 to 4 balls electrical characteristics 128 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 3-2 illustrates an example of power supply decoupling. (1) decoupling capacitors must be placed as closed as possible to the power ball. choose the ground located closest to the power pin for each decoupling capacitor. place the decoupling capacitor ci in a group of 1, 2, or 3 balls; the total must be equal to the decoupling requirement. in case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers. (2) the decoupling capacitor value depends on the board characteristics. figure 3-2. power supply decoupling submit documentation feedback electrical characteristics 129 product preview sram_ldo1 cap_vdd_sram_mpu sram_ldo2 cap_vdd_sram_core bg wkup_ldo vdds_wkup_bg dpll_mpu dpll_core vdds_dpll_dll vdds_sram dpll5 dpll4 vdds_dpll_per video dac vdda_dac omap device vss vssa_dac cvdds_sram ccap_vdd_sram_mpu ccap_vdd_sram_core cvdds_wkup_bgcvdds_dpll_dll cvdds_dpll_per cvdda_dac vdda_dac mmc ios vdds_mmc1 cvdds_mmc1 vdds_mmc1 vdds_sram vdds_wkup_bg vdds_dpll_per vdds_dpll_dll cvdd_wkup cap_vdd_wkup mpu vdd_mpu cvdd_mpu vdd_mpu core vdd_core cvdd_core vdd_core 030-004
3.6 power-up and power-down 3.6.1 power-up sequence omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com this section provides the timing requirements for the omap35 15/03 hardware signals. the following steps give an example of power-up sequence supported by the omap35 15/03 device. 1. vdds and vdds_mem are ramped ensuring a level on the io domain and sys_nrespwron must be low. at the same time, vdds_sram and vdds_wkup_bg can also be ramped. 2. once vdds_wkup_bg rail is stabilized, vdd_core can be ramped. 3. once vdd_core is stabilized, then vdd_mpu can be ramped. 4. vdds_dpll_dll and vdds_dpll_per rails can be ramped at any time during the above sequence. 5. sys_nrespwron can be released as soon as the vdds_pll_dll rail is stabilized, and sys_xtalin and sys_32k clocks are stabilized. 6. during the whole sequence above, sys_nreswarm is held low by omap35 15/03. sys_nreswarm is released after the efuse check has been performed; that is, after sys_nrespwron is released. 7. the other power supplies can then be turned on upon software request. figure 3-3 shows the power-up sequence. note: if an external square clock is provided, it could be started after sys_nrespwron release provided it is clean: no glitch, stable frequency, and duty cycle. 130 electrical characteristics submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 3-3. power-up sequence submit documentation feedback electrical characteristics 131 product preview 030-005 vdds_mem,vdds, vdds_sram vdd_mpu vdd_core vdds_dpll_dll vdds_wkup_bg vdds_mmc1,vdds_mmc1a, vdda_dac , vpp (1) sys_32k sys_nrespwron (2) 1.8 v sys_xtalin sys_nreswarm efuse.rstpwron(internal) vdds_dpll_per ldo3 (internal) (2) 1.8 v 1.8 v 1.8 v
3.6.2 power-down sequence omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the omap35 15/03 device proceeds with the power-down sequence shown in figure 3-4 . figure 3-4. power-down sequence electrical characteristics 132 submit documentation feedback product preview vdds_mem, vdds, vdds_sram vdd_mpu vdd_core vdds_dpll_dll, vdds_dpll_per vdds_wkup_bg vdds_mmc1, vdda_dac sys_32kin sys_nrespwron sys.clk 030-006
4 clock specifications omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the omap35 15/03 device has three external input clocks, a low frequency (sys_32k), a high frequency (sys_xtalin), and an optional (sys_altclk). the omap35 15/03 device has two configurable output clocks, sys_clkout1 and sys_clkout2. figure 4-1 shows the interface to the external clock sources and clock outputs. figure 4-1. clock interface the omap35 15/03 device operation requires the following three input clocks: the 32-khz frequency is used for low frequency operation. it supplies the wake-up domain for operation in lowest power mode (off mode). this clock is provided through the sys_32k pin. the system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54 mhz or other clock source (up to 54 mhz). the system clock input (12, 13, 16.8, 19.2, 26, or 38.4 mhz) is used to generate the main source clock of the omap35 15/03 device. it supplies the dplls as well as several omap modules. the system clock input can be connected to either: ? a crystal oscillator clock managed by sys_xtalin and sys_xtalout. in this case, the sys_clkreq is used as an input (gpin). ? a cmos digital clock through the sys_xtalin pin. in this case, the sys_clkreq is used as an output to request the external system clock. the omap35 15/03 outputs externally two clocks: sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz) at any time. it can be controlled by software or externally using sys_clkreq control. when the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. the off state polarity of sys_clkout1 is programmable. submit documentation feedback clock specifications 133 product preview omap power ic sys_32k sys_altclk sys_clkout1 alternate clock source selectable (54, 48 mhz or other [upto 54 mhz]) to quartz (oscillator output) or unconnected to quartz (oscillator input) or square clock clock request. to square clock source or from peripherals oscillator is used oscillator is bypassed unconnected square clock source to peripherals (from osc_clk: 12,13, 16.8, 19.2, 26, or 38.4 mhz, core_clk [dpll, up to 332 mhz], dpll-96 mhz or dpll-54 mhz outputs with a divider of 1, 2, 4, 8, or 16) gpin to peripherals (from osc_clk: 12, 13,16.8, 19.2, 26, or 38.4 mhz) sys_clkout2 sys_xtalout sys_xtalin sys_clkreq sys_xtaloutsys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq 030-007
4.1 input clock specifications 4.1.1 clock source requirements 4.1.2 external crystal description omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz), core_clk (core dpll output), 96 mhz or 54 mhz. it can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. this output is active only when the core power domain is active. for more information on the omap35 15/03 applications processor clocking structure, see the power, reset, and clock management (prcm) chapter of the omap35x applications processor trm (literature number sprufa5 ). the clock system accepts three input clock sources: 32-khz digital cmos clock crystal oscillator clock or cmos digital clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz) alternate clock (48 or 54 mhz, or other up to 54 mhz) table 4-1 illustrates the requirements to supply a clock to the omap35 15/03 device. table 4-1. clock source requirements pad clock frequency stability duty cycle jitter transition sys_32k 32.768 khz 200 ppm < 20 ns sys_xtalout 12, 13, 16.8, or 19.2 mhz crystal 25 ppm na na na sys_xtalin 12, 13, 16.8, 19.2, 26, or 38.4 mhz square 50 ppm 45% to 55% < 1% < 2.5 ns sys_altclk 48 or 54 mhz 50 ppm 40% to 60% < 1% < 5 ns to supply a 12-, 13-, 16.8-, or 19.2-mhz clock to the omap35 15/03, an external crystal can be connected to the sys_xtalin and sys_xtalout pins. figure 4-2 describes the crystal implementation. figure 4-2. crystal implementation (1) (2) (3) (4) (1) on the pcb, the oscillator components (crystal, foot capacitors, optional r bias and r d ) must be located close to the package. all these components must be routed first with the lowest possible number of board vias. (2) an optional resistor r d can be added in series with the crystal to debug or filter the harmonics; a footprint must be reserved on the pcb for use with 10-mhz crystals and feature low-drive levels. clock specifications 134 submit documentation feedback product preview sys_xtalin sys_xtalout omap device crystal optional r bias optional r d c f2 c f1 030-008
4.1.3 clock squarer input description omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 (3) a 120-k w internal bias resistor r bias is used. the feedback resistor r bias provides negative feedback to the oscillator to put it in the linear operating region; thus oscillation begins when power is applied. (4) c f1 and c f2 represent the total capacitance of the pcb and components excluding the power ic and crystal. their values in fact depend on the crystal datasheet. in the datasheet of the crystal, the frequency is specified at a specific load capacitor value which is the equivalent capacitor of the two capacitors c f1 and c f2 connected to sys_xtalin and sys_xtalout. the frequency of the oscillations depends on the value of the capacitors (10 pf corresponds to a load capacitor of 5 pf for the crystal). the crystal must be in the fundamental mode of operation and parallel resonant. table 4-2 summarizes the required electrical constraints. table 4-2. crystal electrical characteristics name description min typ max unit f p parallel resonance crystal frequency (1) 12, 13, 16.8, or 19.2 mhz c l load capacitance for crystal parallel resonance 5 20 pf esr12 & 13 crystal esr (12 and 13 mhz) (1) 80 w esr16.8 & 19.2 crystal esr (16.8 and 19.2 mhz) (1) 50 w c o crystal shunt capacitance 1 7 pf l m crystal motional inductance for f p = 12 mhz 35 mh c m crystal motional capacitance 5 100 ff dl crystal drive level 0.5 mw r bias internal bias resistor 30 120 300 k w r pdxi pulldown resistor on sys_xtalin when oscillator is 5 k w disabled (1) measured with the load capacitance specified by the crystal manufacturer. this load is defined by the foot capacitances tied in series. if c l = 20 pf, then both foot capacitors will be c f1 = c f2 = 40 pf. parasitic capacitance from package and board must also be taken in account. when selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. table 4-3 details the switching characteristics of the oscillator and the input requirements of the 12-, 13-, 16.8-, or 19.2-mhz input clock. table 4-3. base oscillator switching characteristics name description min typ max unit f p oscillation frequency 12, 13, 16.8, or 19.2 mhz t sx start-up time (1) (2) 8 ms (1) start-up time defined as time interval between oscillator control signal release and sys_xtalin amplitude at 50% of its final value (vdd and vdds supplies ramped and stable). the start-up time can be performed in function of the crystal characteristics. 8-ms minimum only when using the internal oscillator; it is programmable after reset for wake-up. at power-on reset, the time is adjustable using the pin itself. the reset must be released when the oscillator or clock source is stable. before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. the start-up time in this case is about 100 m s. (2) for f p = 12 or 13 mhz: c l = 13.5 pf and l m = 35 mh for f p = 16.8 or 19.2 mhz: c l = 9 pf and l m = 15 mh a 1.8-v cmos clock squarer is another source that can supply a 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-mhz clock to the omap35 15/03. an analog clock squarer function converts a low-amplitude sinusoidal clock into a low-jitter digital signal. it can be connected to input pin sys_xtalin (sys_xtalout unconnected). figure 4-3 illustrates the effective connections. submit documentation feedback clock specifications 135 product preview esr=r m 1 + c 0 c l 2
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 4-3. clock squarer source connection to connect a digital clock source, the oscillator is configured in bypass mode (1) . the sys_clkreq (2) pin is an omap35 15/03 output which can be used to switch the clock source on or off. 1. pin sys_xtalout is not used in this mode. it must be left unconnected. 2. once the system is powered up, the clock squarer source or crystal oscillator source can be applied; however, this affects the performance. the input source must be configured after power up to attain the desired system requirements. table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental mode of operation. table 4-4. base oscillator electrical characteristics (in bypass mode) name description min typ max unit f frequency (1) 12, 13, 16.8, 19.2, 26, or 38.4 mhz t sx start-up time (2) ms r pdxi pulldown resistor on sys_xtalin when oscillator is disabled 5 k w i ddq current consumption on vdds when sys_xtalin = 0 and in 1 m a power-down mode (1) measured with the load capacitance specified by the manufacturer. parasitic capacitance from package and board must also be taken in account. (2) before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. the start-up time in this case is about 100 m s. table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-mhz input clock. table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-mhz input clock squarer timing requirements name description min typ max unit ocs0 1 / t c(xtalin) frequency, sys_xtalin 12, 13, 16.8, 19.2, 26, or 38.4 mhz ocs1 t w(xtalin) pulse duration, sys_xtalin low or high 0.45 * t c(xtalin) 0.55 * t c(xtalin) ns ocs2 t j(xtalin) peak-to-peak jitter (1) , sys_xtalin ?1% 1% ocs3 t r(xtalin) rise time, sys_xtalin 2.5 ns ocs4 t f(xtalin) fall time, sys_xtalin 2.5 ns ocs5 t j(xtalin) frequency stability, sys_xtalin 25 ppm (1) peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300 period samples. the sinusoidal noise is added on top of the vdds supply voltage. clock specifications 136 submit documentation feedback product preview sys_xtalin sys_xtalout omap device sys_clkreq clock squarer source oscillator in bypass mode 030-010
4.1.4 external 32-khz cmos input clock 4.1.5 external sys_altclk cmos input clock omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 4-4. crystal oscillator in bypass mode a 32.768-khz clock signal (often abbreviated to 32-khz) can be supplied by an external 1.8-v cmos signal on pin sys_32k. table 4-6 summarizes the electrical constraints imposed to the clock source. table 4-6. 32-khz input clock source electrical characteristics name description min typ max unit f frequency 32.768 khz c i input capacitance 0.44 pf r i input resistance 0.25 10 6 g w table 4-7 details the input requirements of the 32-khz input clock. table 4-7. 32-khz input clock source timing requirements (1) name description min typ max unit ck0 1 / t c(32k) frequency, sys_32k 32.768 khz ck3 t r(32k) rise time, sys_32k 20 ns ck4 t f(32k) fall time, sys_32k 20 ns ck5 t j(32k) frequency stability, sys_32k 200 ppm (1) see table 3-4 , electrical characteristics, standard lvcmos ios part for sys_32k v ih /v il parameters. figure 4-5. 32-khz cmos clock a 48- or 54-mhz clock signal can be supplied by an external 1.8-v cmos signal on pin sys_altclk. table 4-8 summarizes the electrical constraints imposed by the clock source. table 4-8. 48- or 54-mhz input clock source electrical characteristics name description min typ max unit f frequency , sys_altclk 48 or 54 mhz c i input capacitance 0.74 pf r i input resistance 0.25 10 6 g w table 4-9 details the input requirements of the 48- or 54-mhz input clock. submit documentation feedback clock specifications 137 product preview sys_32k ck0 ck1 ck1 030-012 sys.xtalin ocs0 ocs1 ocs1 030-011
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 4-9. 48- or 54-mhz input clock source timing requirements (1) (2) name description min typ max unit alt0 1 / t c(altclk) frequency, sys_altclk 48 or 54 mhz alt1 t w(altclk) pulse duration, sys_altclk low or 0.40 * t c(altclk) 0.60 * t c(altclk) ns high alt2 t j(altclk) peak-to-peak jitter (1) , sys_altclk ?1% 1% alt3 t r(altclk) rise time, sys_altclk 5 ns alt4 t f(altclk) fall time, sys_altclk 5 ns alt5 t j(altclk) frequency stability, sys_altclk 50 ppm (1) peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300 period samples. the sinusoidal noise is added on top of the vdds supply voltage. (2) see table 3-4 , electrical characteristics, for sys_altclk v ih /v il parameters. figure 4-6. alternate cmos clock 138 clock specifications submit documentation feedback product preview sys_altclk alt0 alt1 alt1 030-013
4.2 output clock specifications omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 two output clocks (pin sys_clkout1 and pin sys_clkout2) are available: sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 mhz) at any time. it can be controlled by software or externally using sys_clkreq control. when the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. the off state polarity of sys_clkout1 is programmable. sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 mhz), core_clk (core dpll output, 332 mhz maximum), apll-96 mhz, or apll-54 mhz. it can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. this output is active only when the core domain is active. table 4-10 summarizes the sys_clkout1 output clock electrical characteristics. table 4-10. sys_clkout1 output clock electrical characteristics name description min typ max unit f frequency 12, 13, 16.8, 19.2, 26, or 38.4 mhz c i load capacitance (1) f(max) = 38.4 mhz 37 pf f(max) = 26 mhz 50 (1) the load capacitance is adapted to a frequency. table 4-11 details the sys_clkout1 output clock timing characteristics. table 4-11. sys_clkout1 output clock switching characteristics name description min typ max unit f 1 / co0 frequency 12, 13, 16.8, 19.2, 26, or 38.4 mhz co1 t w(clkout1) pulse duration, sys_clkout1 low or high 0.40 * 0.60 * ns t c(clkout1) t c(clkout1) co2 t r(clkout1) rise time, sys_clkout1 (1) 5.5 ns co3 t f(clkout1) fall time, sys_clkout1 (1) 5.5 ns (1) with a load capacitance of 25 pf. figure 4-7. sys_clkout1 system output clock table 4-12 summarizes the sys_clkout2 output clock electrical characteristics. table 4-12. sys_clkout2 output clock electrical characteristics name description min typ max unit f frequency, sys_clkout2 322 mhz c l load capacitance (1) f(max) = 166 mhz 2 8 12 pf (1) the load capacitance is adapted to a frequency. table 4-13 details the sys_clkout2 output clock timing characteristics. submit documentation feedback clock specifications 139 product preview sys_clkout co0 co1 co1 030-014
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 4-13. sys_clkout2 output clock switching characteristics name description min typ max unit f 1 / co0 frequency 322 mhz co1 t w(clkout2) pulse duration, sys_clkout2 low or high 0.40 * t c(clkout2) 0.60 * t c(clkout2) ns co2 t r(clkout2) rise time, sys_clkout2 (1) 3.7 ns co3 t f(clkout2) fall time, sys_clkout2 (1) 4.3 ns (1) with a load capacitance of 12 pf. figure 4-8. sys_clkout2 system output clock 140 clock specifications submit documentation feedback product preview sys_clkout co0 co1 co1 030-015
4.3 dpll and dll specifications 4.3.1 digital phase-locked loop (dpll) omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the omap35 15/03 integrates six dplls and a dll. the prm and cm drive five of them, while the sixth ( not supported) is controlled by the display controller. the five main dplls are: dpll1 (mpu) dpll2 ( not supported on omap3515/03 devices) dpll3 (core) dpll4 (peripherals) dpll5 (second peripherals dpll) figure 4-9 illustrates the dll and dpll implementation. (1) dpll2 is not supported on omap3515/03 devices. figure 4-9. dpll and dll implementation for more information on the omap35 30/25 applications processor dplls and clocking structure, see the power, reset, and clock management (prcm) chapter of the omap35x applications processor trm (literature number sprufa5 ). the dpll provides all interface clocks and some functional clocks (such as the processor clocks) of the omap35 15/03 device. dpll1 and dpll2 get an always-on clock used to produce the synthesized clock. they get a high-speed bypass clock used to switch the dpll output clock on this high-speed clock during bypass mode. the high-speed bypass clock is an l3 divided clock (programmable by 1 or 2) that saves dpll processor power consumption when the processor does not need to run faster than the l3 clock speed, or optimizes performance during frequency scaling. each dpll synthesized frequency is set by programming m (multiplier) and n (divider) factors. in addition, all dpll outputs can be controlled by an independent divider (m2 to m6). the clock generating dplls of the omap35 15/03 device have following features: independent power domain per dpll controlled by clock-manager (cm) submit documentation feedback clock specifications 141 product preview omap dll vdds_dpll_dll power rail dpll4 dpll1 dpll2 dpll3 vdds_dpll_per dpll5 030-016
4.3.1.1 dpll1 (mpu) 4.3.1.2 dpll3 (core) 4.3.1.3 dpll4 (peripherals) 4.3.1.4 dpll5 (second peripherals dpll) 4.3.2 delay-locked loops (dll) omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com fed with always-on system clock with independent gating control per dpll analog part supplied through dedicated power supply (1.8 v) and an embedded ldo to get rid of 1-mhz noise up to five independent output dividers for simultaneous generation of multiple clock frequencies dpll1 is located in the mpu subsystem and supplies all clocks of the subsystem. all mpu subsystem clocks are internally generated in the subsystem. when the core domain is on, it can use the dpll3 (core dpll) output as a high-frequency bypass input clock. dpll3 supplies all interface clocks and also a few module functional clocks. it can be also source of the emulation trace clock. it is located in the core domain area. all interface clocks and a few module functional clocks are generated in the cm. when the core domain is on, it can be used as a bypass input to dpll1 and dpll2. dpll4 generates clocks for the peripherals. it supplies five clock sources: 96-mhz functional clocks to subsystems and peripherals, 54 mhz to tv dac, display functional clock, camera sensor clock, and emulation trace clock. it is located in the core domain area. all interface clocks and few module functional clocks are generated in the cm. its outputs to the dss, per, and emu domains are propagated with always-on clock trees. dpll5 supplies the 120-mhz functional clock to the cm. the sdrc includes analog-controlled delay technology for interfacing high-speed mobile ddr memory components. for more information, see the sdrc-gpmc chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. a dll is a calibration module used on dynamic track of voltage and temperature variations, as well as to compensate the silicon process dispersion. the sdrc dll has four modes of operation: 1. application mode 0: used to generate 72 delay 2. application mode 1: used to generate 90 delay 3. modemaxdelay: used for low frequency operation where we do not have the requirement of accurate 72 or 90 phase shift 4. idle mode: a low-power state that allows the dll to gain lock quickly on exit from this mode 142 clock specifications submit documentation feedback product preview
4.3.3 dplls and dll characteristics omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 several specifications characterize the six dplls. table 4-14 summarizes the dpll characteristics and assumes testing over recommended operating conditions. table 4-14. dpll characteristics name parameter min typ max unit comments (1) vdds_dpll_per 1.71 1.8 1.89 v at module pins (+5%, ?10%) vdds_dpll_dll 1.71 1.8 1.89 v t j junction temperature ?40 25 107 c will not unlock after lock over this range for slow temperature drifts f input input reference frequency (2) 0.75 65 mhz finp f internal internal reference frequency 0.75 2.1 mhz freqsel3 = 0; fint = finp/(n+1) 7.5 21 mhz freqsel3 = 1; fint = finp/(n+1) f output clkout output frequency 25 900 mhz f output*2 clkoutx2 output 50 1800 mhz frequency t lock frequency lock time (3) 71.4 200 m s 150 fint cycles; freqsel3 = 0 37.1 104 m s 780 fint cycles; freqsel3 = 1 p lock phase lock time 166.7 466.7 m s 350 fint cycles; freqsel3 = 0 46.7 130.7 m s 980 fint cycles; freqsel3 = 1 t relock relock time ? frequency 4.8 13.3 m s 10 fint cycles lock (4) lowcurrstby = 0; freqsel3 = 0 4.8 13.3 m s 100 fint cycles lowcurrstby = 0; freqsel3 = 1 19 53.3 m s 40 fint cycles lowcurrstby = 1; freqsel3 = 0 19 53.3 m s 400 fint cycles lowcurrstby = 1; freqsel3 = 1 p relock relock time ? phase lock (4) 71.4 200 m s 150 fint cycles lowcurrstby = 0; freqsel3 = 0 11.9 33.3 m s 250 fint cycles lowcurrstby = 0; freqsel3 = 1 95.2 266.7 m s 200 fint cycles lowcurrstby = 1; freqsel3 = 0 26.7 74.7 m s 560 fint cycles lowcurrstby = 1; freqsel3 = 1 table 4-15 show s the dpll1 clock frequency ranges. note: the dpll1 clock frequency ranges depend on the v dd1 (vdd_mpu) operating point. (1) f reqsel needs to be programmed accordingly to reference clock and dpll divider (register setting), lowcurrstdby depends on the targeted dpll power state (dynamic). lowcurrstdby = 0 then dpll is in normal mode lowcurrstdby = 1 then dpll is in low-power mode (2) input frequencies below 0.75 mhz are possible with performance penalty. (3) maximum frequency for nominal conditions. speed binning possible above fmax. (4) relock time assumes typical operating conditions, 4 c maximum temperature drift (see the functional specification for more detailed information). submit documentation feedback clock specifications 143 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 4-15. dpll1 clock frequency ranges clock signal description max unit dpll1_alwon dpll1 reference clock input, tbd mhz _fclk taken from prm sys_clk. dpll1 high-frequency bypass dpll1_fclk clock input, taken from cm tbd mhz core_clk. opp5 600 mhz opp4 550 mhz dpll1 internal clock signal, dpll1: generated through dpll1 opp3 500 mhz clkoutx2 multiplier and divider. opp2 500 mhz opp1 500 mhz opp5 600 mhz opp4 550 mhz dpll1 output clock, generated mpu_clk opp3 500 mhz from clkout_m2x2. opp2 250 mhz opp1 125 mhz table 4-16 through table 4-18 show the dpll3 clock frequency ranges. note: the dpll3 clock frequency ranges depend on the vdd2 (vdd_core) operating point and the l3 clock speed configuration. table 4-16. dpll3 clock frequency ranges, vdd2 opp3 config 1 config 2 config 3 (166 mhz) (133 mhz) (100 mhz) unit clock signal description min max min max min max dpll3 input reference clock, generated dpll3_alwon_fclk tbd tbd tbd tbd tbd tbd mhz by prm. dpll3 internal clock signal, generated dpll3: clkoutx2 50 664 50 532 50 400 mhz through dpll3 multiplier and divider. dpll3 internal clock signal, generated dpll3: clkout 25 332 25 266 25 200 mhz by dividing dpll3 clkoutx2 by 2. output of clock manager (cm), cm: core_clk generated directly from dpll3 - 332 - 266 - 200 mhz clkout_m2. output of clock manager (cm), cm: l3_iclk generated using dpll3 clkout_m2x2 - 166 - 133 - 100 mhz and divider. output of clock manager (cm), cm: l4_iclk generated using cm l3_iclk and - 83 - 66.5 - 50 mhz divider. sgx input clock, taken from cm sgx - 110.67 - 88.67 - 66.67 mhz core_clk. sdrc input clock, taken from cm sdrc - 166 - 133 - 100 mhz l3_iclk. gpmc input clock, taken from cm gpmc - 83 - 66.5 - 100 mhz l3_iclk. table 4-17. dpll3 clock frequency ranges, vdd2 opp2 config 1 config 2 (83 mhz) (100 mhz) unit clock signal description min max min max dpll3 input reference clock, generated by dpll3_alwon_fclk tbd tbd tbd tbd mhz prm. clock specifications 144 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 4-17. dpll3 clock frequency ranges, vdd2 opp2 (continued) config 1 config 2 (83 mhz) (100 mhz) unit clock signal description min max min max dpll3 internal clock signal, generated through dpll3: clkoutx2 50 664 50 400 mhz dpll3 multiplier and divider. dpll3 internal clock signal, generated by dpll3: clkout 25 332 25 200 mhz dividing dpll3 clkoutx2 by 2. output of clock manager (cm), generated cm: core_clk - 166 - 200 mhz directly from dpll3 clkout_m2. output of clock manager (cm), generated using cm: l3_iclk - 83 - 100 mhz dpll3 clkout_m2x2 and divider. output of clock manager (cm), generated using cm: l4_iclk - 41.5 - 50 mhz cm l3_iclk and divider. sgx sgx input clock, taken from cm core_clk. - 55.53 - 66.67 mhz sdrc sdrc input clock, taken from cm l3_iclk. - 83 - 100 mhz gpmc gpmc input clock, taken from cm l3_iclk. - 83 - 50 mhz table 4-18. dpll3 clock frequency ranges, vdd2 opp1 config 1 (40 mhz) unit clock signal description min max dpll3_alwon_fclk dpll3 input reference clock, generated by prm. tbd tbd mhz dpll3 internal clock signal, generated through dpll3 dpll3: clkoutx2 50 664 mhz multiplier and divider. dpll3 internal clock signal, generated by dividing dpll3 dpll3: clkout 25 332 mhz clkoutx2 by 2. output of clock manager (cm), generated directly from dpll3 cm: core_clk - 83 mhz clkout_m2. output of clock manager (cm), generated using dpll3 cm: l3_iclk - 41.5 mhz clkout_m2x2 and divider. output of clock manager (cm), generated using cm l3_iclk cm: l4_iclk - 20.75 mhz and divider. sgx sgx input clock, taken from cm core_clk. - n/a mhz sdrc sdrc input clock, taken from cm l3_iclk. - 41.5 mhz gpmc gpmc input clock, taken from cm l3_iclk. - 41.5 mhz table 4-19 summarizes the dll characteristics. table 4-19. dll characteristics parameter min nom max unit comments supply voltage vdds_dpll_dll 1.71 1.8 1.89 v junction operating temperature ?40 25 107 c input clock frequency 66 120 133 mhz application mode 0 83 120 166 application mode 1 input load (1) 15 ff lock time (2) 500 clocks relock time 500 ns idle to modemaxdelay (1) this parameter is design goal and is not tested on silicon. (2) lock signal would go high from power down within 500 clocks. lock signal switches to low state when the input clock is switched off after 3 m s. submit documentation feedback clock specifications 145 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 4-19. dll characteristics (continued) parameter min nom max unit comments (mode transitions through idle mode) 150 372 clocks idle to application mode 1 or 0 1 2 m s idle to application mode @133 mhz 1 1.5 m s idle to application mode @166 mhz clock specifications 146 submit documentation feedback product preview
4.3.4 dpll and dll noise isolation omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the dpll and dll require dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. guard rings are added to the cell to isolate it from substrate noise injection. the vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails. the maximum input noise level allowed is 30 mv pp for frequencies below 1 mhz. figure 4-10 illustrates an example of a noise filter. (1) dpll2 is not supported on omap3515/03 devices. figure 4-10. dpll and dll noise filter (1) table 4-20 specifies the noise filter requirements. table 4-20. dpll and dll noise filter requirements name min typ max unit filtering capacitor 100 nf (1) the capacitors must be inserted between power and ground as close as possible. (2) this circuit is provided only as an example. (3) the filter must be located as close as possible to the device. (4) no filtering required if noise is below 10 mv pp . submit documentation feedback clock specifications 147 product preview omap device dpll_mpu dpll2 dpll_core dll dpll5 dpll4 vdds_dpll_dll vdds_dpll_per c noise filter c noise filter 030-017
5 video dac specifications 5.1 interface description omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com a dual-display interface equips the omap35 15/03 processor. this display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (tv-set). two (one per channel) 10-bit current steering dacs are inserted between the dss and the tv set to generate the video analog signal. one of the video dacs also includes tv detection and power-down mode. figure 5-1 illustrates the omap35 15/03 dac architecture. for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. figure 5-1. video dac architecture the following paragraphs detail the 10-bit dac interface pinout, static and dynamic specifications, and noise requirements. the operating conditions and absolute maximum ratings are detailed in table 5-2 and table 5-4 . table 5-1 summarizes the external pins of the video dac. table 5-1. external pins of 10-bit video dac pin name i/o description tv_out1 o tv analog output composite dac1 video output. an external resistor is connected between this node and tv_vfb1. the nominal value of rout1 is 1650 w . finally, note that this is the output node that drives the load (75 w ). video dac specifications 148 submit documentation feedback product preview omap device dss tv_vref din1[9:0] vssa_dac vdda_dac video dac 1 tv dct video dac 2 tvout buffer din2[9:0] tvout buffer tvout buffer tv_vfb1 tv_out1 c bg tv_out2 tv_vfb2 v_ref 030-018 r out1 r out2
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 5-1. external pins of 10-bit video dac (continued) pin name i/o description tv_out2 o tv analog output s-video dac2 video output. an external resistor is connected between this node and tv_vfb2. the nominal value of rout2 is 1650 w . finally, note that this is the output node that drives the load (75 w ). tv_vref i reference output voltage from internal a decoupling capacitor (cbg) needs to be connected for optimum bandgap performance. tv_vfb1 o amplifier feedback node amplifier feedback node. an external resistor is connected between this node and tv_out1. the nominal value of rout1 is 1650 w (1%). tv_vfb2 o amplifier feedback node amplifier feedback node. an external resistor is connected between this node and tv_out2. the nominal value of rout2 is 1650 w (1%). submit documentation feedback video dac specifications 149 product preview
5.2 electrical specifications over recommended operating conditions omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com (t min to t max , vdda_dac = 1.8 v, r out1/2 = 1650 w , r load = 75 w , unless otherwise noted) table 5-2. dac ? static electrical specification parameter conditions/assumptions min typ max unit r resolution 10 bits dc accuracy inl (1) integral nonlinearity ?1 1 lsb dnl (2) differential nonlinearity ?1 1 lsb analog output - full-scale output voltage r load = 75 w 0,7 0.88 1 v - output offset voltage 50 mv - output offset voltage drift 20 mv/ c - gain error ?17 19 % fs r vout output impedance 67.5 75 82.5 w reference v ref reference voltage range 0.525 0.55 0.575 v - reference noise density 100-khz reference noise 129 bandwidth r set full-scale current adjust resistor 3700 4000 4200 w p srr reference psrr (3) (up to 6 mhz) 40 db power consumption i vdda-up analog supply current (4) 2 channels, no load 8 ma - analog supply driving a 75- w load 2 channels 50 ma (rms) i vdda-up (peak) peak analog supply current: lasts less than 1 ns 60 ma i vdd-up digital supply current (5) measured at f clk = 54 mhz, f out 2 ma = 2 mhz sine wave, vdd = 1.3 v i vdd-up (peak) peak digital supply current (6) lasts less than 1 ns 2.5 ma i vdda-down analog power at power-down t = 30 c, vdda = 1.8 v 1.5 ma i vdd-down digital power at power-down t = 30 c, vdd = 1.3 v 1 ma (1) the inl is measured at the output of the dac (accessible at an external pin during bypass mode). (2) the dnl is measured at the output of the dac (accessible at an external pin during bypass mode). (3) assuming a capacitor of 0.1 m f at the tv_ref node. (4) the analog supply current i vdda is directly proportional to the full-scale output current ifs and is insensitive to f clk (5) the digital supply current i vdd is dependent on the digital input waveform, the dac update rate f clk , and the digital supply vdd. (6) the peak digital supply current occurs at full-scale transition for duration less than 1 ns. video dac specifications 150 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 (t min to t max , vdda_dac = 1.8 v, r out1/2 = 1650 w , r load = 75 w , unless otherwise noted) table 5-3. video dac ? dynamic electrical specification parameter conditions/assumptions min typ max unit f clk (1) output update rate equal to input clock frequency 54 mhz clock jitter rms clock jitter required in order to assure 40 ps 10-bit accuracy attenuation at 5.1 mhz corner frequency for signal 0.1 0.5 1.5 db attenuation at 54 mhz (1) image frequency 25 30 33 db t st output settling time time from the start of the output transition to 85 ns output within 1 lsb of final value. t rout output rise time measured from 10% to 90% of full-scale 25 ns transition t fout output fall time measured from 10% to 90% of full-scale 25 ns transition bw signal bandwidth 6 mhz differential gain (2) 1.5% differential phase (2) 1 deg. sfdr within bandwidth f clk = 54 mhz, f out = 1 mhz 45 db snr signal-to-noise ratio f clk = 54 mhz, f out = 1 mhz 55 (3) db 1 khz to 6 mhz bandwidth psrr power supply rejection ratio up to 6 mhz 20 (4) db crosstalk between the two video ?50 ?40 db channels (1) for internal input clock information, for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. (2) the differential gain and phase value is for dc coupling. note that there is degradation for the ac coupling. (3) the snr value is for dc coupling. note that there is a 6-db degradation for ac coupling. (4) the pssr value is for dc coupling. note that there is a 10-db degradation for ac coupling. submit documentation feedback video dac specifications 151 product preview
5.3 analog supply (vdda_dac) noise requirements supply variation as shown in the following equation: omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in order to assure 10-bit accuracy of the dac analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section. the dac power supply rejection ratio is defined as the relative variation of the full-scale output current divided by the supply variation. thus, it is expressed in percentage of full-scale range (fsr) per volt of depending on frequency, the psrr is defined in table 5-4 . table 5-4. video dac ? power supply rejection ratio supply noise frequency psrr % fsr/v 0 to 100 khz 1 > 100 khz the rejection decreases 20 db/dec. example: at 1 mhz the psrr is 10% of fsr/v a graphic representation is shown in figure 5-2 . figure 5-2. video dac ? power supply rejection ratio to ensure that the dac sfdr specification is met, the psrr values and the clock jitter requirements translate to the following limits on vdda_dac (for the video dac). the maximum peak-to-peak noise on vdda (ripple) is defined in table 5-5 : table 5-5. video dac ? maximum peak-to-peak noise on vdda_dac tone frequency maximum peak-to-peak noise on vdda_dac 0 to 100 khz < 30 mvpp > 100 khz decreases 20 db/dec. example: at 1 mhz the maximum is 3 mvpp the maximum noise spectral density (white noise) is defined in table 5-6 : table 5-6. video dac ? maximum noise spectral density supply noise bandwidth maximum supply noise density 0 to 100 khz < 20 m v / ? hz > 100 khz decreases 20 db/dec. example: at 1 mhz the maximum noise density is 2 m / ? hz video dac specifications 152 submit documentation feedback product preview ac outfs out dac v i i psrr d = 100 % fsr v 1 100 khz 1 mhz 10 psrr (% fsr/v) f first pole ofdac output load 030-019
5.4 external component value choice omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 because the dac psrr deteriorates at a rate of 20 db/dec after 100 khz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: section 5.4 , external component value choice). the full-scale output voltage v outmax is regulated by the reference amplifier, and is set by an internal resistor r set . i outmax can be expressed as: i outmax = i ref /8 * (63 + 15/16) where: v ref = 0.5v i ref = v ref /r set the output current i out appearing at dac output is a function of both the input code and i outmax and can be expressed as: i out = (dac_code/1023) * i outmax where: dac_code = 0 to 1023 is the dac input code in decimal. the output voltage is: v out = i out *n* r cable where: (n = amplifier gain = 21) r cable = 75 w (cable typical impedance) the tv-out buffer requires a per channel external resistors: r out1/2 . the equation below can be used to select different resistor values (if necessary): r out = (n+1) r cable = 1650 w recommended parameter values are: table 5-7. video dac ? recommended external components values recommended value unit c bg 100 nf r out1/2 1650 w in order to limit the reference noise bandwidth and to suppress transients on v ref , it is necessary to connect a large decoupling capacitor bg ) between the tv_vref and vssa_dac pins. submit documentation feedback video dac specifications 153 product preview
6 timing requirements and switching characteristics 6.1 timing test conditions 6.2 interface clock specifications 6.2.1 interface clock terminology 6.2.2 interface clock frequency 6.2.3 clock jitter specifications 6.2.4 clock duty cycle error omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com all timing requirements and switching characteristics are valid over the recommended operating conditions of table 3-3 , unless otherwise specified. the interface clock is used at the system level to sequence the data and/or control transfers accordingly with the interface protocol. the two interface clock characteristics are: the maximum clock frequency the maximum operating frequency the interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. this frequency defines the maximum limit supported by the omap35 15/03 ic and doesn?t take into account any system consideration (pcb, peripherals). the system designer will have to consider these system considerations and omap35 15/03 ic timings characteristics as well, to define properly the maximum operating frequency, which corresponds to the maximum frequency supported to transfer the data on this interface. jitter is a phase noise, which may alter different characteristics of a clock signal. the jitter specified in this document is the time difference between the typical cycle period and the actual cycle period affected by noise sources on the clock. the cycle (or period) jitter terminology identifies this type of jitter. figure 6-1. cycle (or period) jitter the duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration and the cycle time of a clock signal. timing requirements and switching characteristics 154 submit documentation feedback product preview cycle (or period) jitter t n-1 t n t n+1 max. cycle jitter = max (t ) i min. cycle jitter = min (t ) i jitter standard deviation (or rms jitter) = standard deviation (t ) i 030-020
6.3 timing parameters omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with jedec standard 100. to shorten the symbols, some pin names and other related terminologies have been abbreviated as follows: table 6-1. timing parameters lowercase subscripts symbols parameter c cycle time (period) d delay time dis disable time en enable time h hold time su setup time start start bit t transition time v valid time w pulse duration (width) x unknown, changing, or don?t care level h high l low v valid iv invalid ae active edge fe first edge le last edge z high impedance submit documentation feedback timing requirements and switching characteristics 155 product preview
6.4 external memory interfaces 6.4.1 general-purpose memory controller (gpmc) 6.4.1.1 gpmc/nor flash interface synchronous timing omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the omap35 15/03 processor includes the following external memory interfaces: general-purpose memory controller (gpmc) sdram controller (sdrc) the gpmc is the omap35 15/03 unified memory controller used to interface external memory devices such as: asynchronous sram-like memories and asic devices asynchronous page mode and synchronous burst nor flash nand flash table 6-3 and table 6-4 assume testing over the recommended operating conditions (see figure 6-2 through figure 6-5 ) and electrical characteristic conditions. table 6-2. gpmc/nor flash synchronous mode timing conditions timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance 15.94 pf table 6-3. gpmc/nor flash interface timing requirements ? synchronous mode no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max f12 t su(dv-clkh) setup time, read gpmc_d[15:0] 1.9 1.9 3.2 ns valid before gpmc_clk high f13 t h(clkh-dv) hold time, read gpmc_d[15:0] 2.5 2.5 2.5 ns valid after gpmc_clk high f21 t su(waitv-clkh) setup time, gpmc_waitx (1) valid 1.9 1.9 3.2 ns before gpmc_clk high f22 t h(clkh-waitv) hold time, gpmc_waitx (1) valid 2.5 2.5 2.5 ns after gpmc_clk high (1) wait monitoring support is limited to a waitmonitoringtime value > 0. for a full description of wait monitoring feature, see the omap35x technical reference manual (literature number table 6-4. gpmc/nor flash interface switching characteristics ? synchronous mode no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max f0 t c(clk) cycle time (15) , output 10 12.05 25 ns clock gpmc_clk period f1 t w(clkh) typical pulse duration, 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) ns output clock gpmc_clk high f1 t w(clkl) typical pulse duration, 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) 0.5 p (12) ns output clock gpmc_clk low t dc(clk) duty cycle error, output ?500 500 ?602 602 ?1250 1250 ps clk gpmc_clk timing requirements and switching characteristics 156 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-4. gpmc/nor flash interface switching characteristics ? synchronous mode (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max t j(clk) jitter standard 33.3 33.3 33.3 ps deviation (16) , output clock gpmc_clk t r(clk) rise time, output clock 1.6 2 2 ns gpmc_clk t f(clk) fall time, output clock 1.6 2 2 ns gpmc_clk t r(do) rise time, output data 2 2 2 ns t f(do) fall time, output data 2 2 2 ns f2 t d(clkh-ncsv) delay time, gpmc_clk f (6) ? 1.9 f (6) + 3.3 f (6) ? 1.8 f (6) + 4.1 f (6) ? 2.6 f (6) + 4.9 ns rising edge to gpmc_ncsx (11) transition f3 t d(clkh-ncsiv) delay time, gpmc_clk e (5) ? 1.9 e (5) + 3.3 e (5) ? 1.8 e (5) + 4.1 e (5) ? 2.6 e (5) + 4.9 ns rising edge to gpmc_ncsx (11) invalid f4 t d(addv-clk) delay time, address bus b (2) ? 4.1 b (2) + 2.1 b (2) ? 4.1 b (2) + 2.1 b (2) ? 4.9 b (2) + 2.6 ns valid to gpmc_clk first edge f5 t d(clkh-addiv) delay time, gpmc_clk ?2.1 ?2.1 ?2.6 ns rising edge to gpmc_a[16:1] invalid f6 t d(nbev-clk) delay time, b (2) ? 1.1 b (2) + 2.1 b (2) ? 0.9 b (2) + 1.9 b (2) ? 2.6 b (2) + 2.6 ns gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_clk first edge f7 t d(clkh-nbeiv) delay time, gpmc_clk d (4) ? 2.1 d (4) + 1.1 d (4) ? 1.9 d (4) + 0.9 d (4) ? 2.6 d (4) + 2.6 ns rising edge to gpmc_nbe0_cle, gpmc_nbe1 invalid f8 t d(clkh-nadv) delay time, gpmc_clk g (7) ? 1.9 g (7) + 4.1 g (7) ? 2.1 g (7) + 4.1 g (7) ? 2.6 g (7) + 4.9 ns rising edge to gpmc_nadv_ale transition f9 t d(clkh-nadviv) delay time, gpmc_clk d (4) ? 1.9 d (4) + 4.1 d (4) ? 2.1 d (4) + 4.1 d (4) ? 2.6 d (4) + 4.9 ns rising edge to gpmc_nadv_ale invalid f10 t d(clkh-noe) delay time, gpmc_clk h (8) ? 2.1 h (8) + 2.1 h (8) ? 2.1 h (8) + 2.1 h (8) ? 2.6 h (8) + 4.9 ns rising edge to gpmc_noe transition f11 t d(clkh-noeiv) delay time, gpcm rising e (5) ? 2.1 e (5) + 2.1 e (5) ? 2.1 e (5) + 2.1 e (5) ? 2.6 e (5) + 4.9 ns edge to gpmc_noe invalid f14 t d(clkh-nwe) delay time, gpmc_clk i (9) ? 1.9 i (9) + 4.1 i (9) ? 2.1 i (9) + 4.1 i (9) ? 2.6 i (9) + 4.9 ns rising edge to gpmc_nwe transition f15 t d(clkh-data) delay time, gpmc_clk j (10) ? 2.1 j (10) + 1.1 j (10) ? 1.9 j (10) + 0.9 j (10) ? 2.6 j (10) + 2.6 ns rising edge to data bus transition f17 t d(clkh-nbe) delay time, gpmc_clk j (10) ? 2.1 j (10) + 1.1 j (10) ? 1.9 j (10) + 0.9 j (10) ? 2.6 j (10) + 2.6 ns rising edge to gpmc_nbex_cle transition f18 t w(ncsv) pulse duration, read a (1) a (1) a (1) ns gpmc_ncsx (11) write a (1) a (1) a (1) ns low f19 t w(nbev) pulse duration, read c (3) c (3) c (3) ns gpmc_nbe0_cle, write c (3) c (3) c (3) ns gpmc_nbe1 low f20 t w(nadvv) pulse duration, read k (13) k (13) k (13) ns gpmc_nadv_ale write k (13) k (13) k (13) ns low submit documentation feedback timing requirements and switching characteristics 157 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-4. gpmc/nor flash interface switching characteristics ? synchronous mode (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max f23 t d(clkh-iodir) delay time, gpmc_clk h (8) ? 2.1 h (8) + 4.1 h (8) ? 2.1 h (8) + 4.1 h (8) ? 2.6 h (8) + 4.9 ns rising edge to gpmc_io_dir high (in direction) f24 t d(clkh-iodiv) delay time, gpmc_clk m (17) ? 2.1 m (17) + 4.1 m (17) ? 2.1 m (17) + 4.1 m (17) ? 2.6 m (17) + 4.9 ns rising edge to gpmc_io_dir low (out direction) (1) for single read: a = (csrdofftime ? csontime) * (timeparagranularity + 1) * gpmc_fclk period for burst read: a = (csrdofftime ? csontime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk period for burst write: a = (cswrofftime ? csontime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk period with n being the page burst access number. (2) b = clkactivationtime * gpmc_fclk (3) for single read: c = rdcycletime * (timeparagranularity + 1) * gpmc_fclk for burst read: c = (rdcycletime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk for burst write: c = (wrcycletime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk with n being the page burst access number. (4) for single read: d = (rdcycletime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk for burst read: d = (rdcycletime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk for burst write: d = (wrcycletime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk (5) for single read: e = (csrdofftime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk for burst read: e = (csrdofftime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk for burst write: e = (cswrofftime ? accesstime) * (timeparagranularity + 1) * gpmc_fclk (6) for ncs falling edge (cs activated): ? case gpmcfclkdivider = 0: ? f = 0.5 * csextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? f = 0.5 * csextradelay * gpmc_fclk if (clkactivationtime and csontime are odd) or (clkactivationtime and csontime are even) ? f = (1 + 0.5 * csextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? f = 0.5 * csextradelay * gpmc_fclk if ((csontime ? clkactivationtime) is a multiple of 3) ? f = (1 + 0.5 * csextradelay) * gpmc_fclk if ((csontime ? clkactivationtime ? 1) is a multiple of 3) ? f = (2 + 0.5 * csextradelay) * gpmc_fclk if ((csontime ? clkactivationtime ? 2) is a multiple of 3) (7) for adv falling edge (adv activated): ? case gpmcfclkdivider = 0: ? g = 0.5 * advextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? g = 0.5 * advextradelay * gpmc_fclk if (clkactivationtime and advontime are odd) or (clkactivationtime and advontime are even) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? g = 0.5 * advextradelay * gpmc_fclk if ((advontime ? clkactivationtime) is a multiple of 3) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk if ((advontime ? clkactivationtime ? 1) is a multiple of 3) ? g = (2 + 0.5 * advextradelay) * gpmc_fclk if ((advontime ? clkactivationtime ? 2) is a multiple of 3) for adv rising edge (adv deactivated) in reading mode: ? case gpmcfclkdivider = 0: ? g = 0.5 * advextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? g = 0.5 * advextradelay * gpmc_fclk if (clkactivationtime and advrdofftime are odd) or (clkactivationtime and advrdofftime are even) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? g = 0.5 * advextradelay * gpmc_fclk if ((advrdofftime ? clkactivationtime) is a multiple of 3) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk if ((advrdofftime ? clkactivationtime ? 1) is a multiple of 3) ? g = (2 + 0.5 * advextradelay) * gpmc_fclk if ((advrdofftime ? clkactivationtime ? 2) is a multiple of 3) for adv rising edge (adv deactivated) in writing mode: ? case gpmcfclkdivider = 0: ? g = 0.5 * advextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? g = 0.5 * advextradelay * gpmc_fclk if (clkactivationtime and advwrofftime are odd) or (clkactivationtime and advwrofftime are even) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: timing requirements and switching characteristics 158 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 ? g = 0.5 * advextradelay * gpmc_fclk if ((advwrofftime ? clkactivationtime) is a multiple of 3) ? g = (1 + 0.5 * advextradelay) * gpmc_fclk if ((advwrofftime ? clkactivationtime ? 1) is a multiple of 3) ? g = (2 + 0.5 * advextradelay) * gpmc_fclk if ((advwrofftime ? clkactivationtime ? 2) is a multiple of 3) (8) for oe falling edge (oe activated) / io dir rising edge (data bus input direction): ? case gpmcfclkdivider = 0: ? h = 0.5 * oeextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? h = 0.5 * oeextradelay * gpmc_fclk if (clkactivationtime and oeontime are odd) or (clkactivationtime and oeontime are even) ? h = (1 + 0.5 * oeextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? h = 0.5 * oeextradelay * gpmc_fclk if ((oeontime ? clkactivationtime) is a multiple of 3) ? h = (1 + 0.5 * oeextradelay) * gpmc_fclk if ((oeontime ? clkactivationtime ? 1) is a multiple of 3) ? h = (2 + 0.5 * oeextradelay) * gpmc_fclk if ((oeontime ? clkactivationtime ? 2) is a multiple of 3) for oe rising edge (oe deactivated): ? gpmcfclkdivider = 0: ? h = 0.5 * oeextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? h = 0.5 * oeextradelay * gpmc_fc if (clkactivationtime and oeofftime are odd) or (clkactivationtime and oeofftime are even) ? h = (1 + 0.5 * oeextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? h = 0.5 * oeextradelay * gpmc_fclk if ((oeofftime ? clkactivationtime) is a multiple of 3) ? h = (1 + 0.5 * oeextradelay) * gpmc_fclk if ((oeofftime ? clkactivationtime ? 1) is a multiple of 3) ? h = (2 + 0.5 * oeextradelay) * gpmc_fclk if ((oeofftime ? clkactivationtime ? 2) is a multiple of 3) (9) for we falling edge (we activated): ? case gpmcfclkdivider = 0: ? i = 0.5 * weextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? i = 0.5 * weextradelay * gpmc_fclk if (clkactivationtime and weontime are odd) or (clkactivationtime and weontime are even) ? i = (1 + 0.5 * weextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? i = 0.5 * weextradelay * gpmc_fclk if ((weontime ? clkactivationtime) is a multiple of 3) ? i = (1 + 0.5 * weextradelay) * gpmc_fclk if ((weontime ? clkactivationtime ? 1) is a multiple of 3) ? i = (2 + 0.5 * weextradelay) * gpmc_fclk if ((weontime ? clkactivationtime ? 2) is a multiple of 3) for we rising edge (we deactivated): ? case gpmcfclkdivider = 0: ? i = 0.5 * weextradelay * gpmc_fclk ? case gpmcfclkdivider = 1: ? i = 0.5 * weextradelay * gpmc_fclk if (clkactivationtime and weofftime are odd) or (clkactivationtime and weofftime are even) ? i = (1 + 0.5 * weextradelay) * gpmc_fclk otherwise ? case gpmcfclkdivider = 2: ? i = 0.5 * weextradelay * gpmc_fclk if ((weofftime ? clkactivationtime) is a multiple of 3) ? i = (1 + 0.5 * weextradelay) * gpmc_fclk if ((weofftime ? clkactivationtime ? 1) is a multiple of 3) ? i = (2 + 0.5 * weextradelay) * gpmc_fclk if ((weofftime ? clkactivationtime ? 2) is a multiple of 3) (10) j = gpmc_fclk period (11) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (12) p = gpmc_clk period (13) for read: k = (advrdofftime ? advontime) * (timeparagranularity + 1) * gpmc_fclk for write: k = (advwrofftime ? advontime) * (timeparagranularity + 1) * gpmc_fclk (14) gpmc_fclk is general-purpose memory controller internal functional clock. (15) related to the gpmc_clk output clock maximum and minimum frequencies programmable in the i/f module by setting the gpmc_config1_csx configuration register bit field gpmcfclkdivider. (16) the jitter probability density can be approximated by a gaussian function. (17) m = (rdcycletime - accesstime) * (timeparagranularity + 1) * gpmc_fclk above m parameter expression is given as one example of gpmc programming. io dir signal will go from in to out after both rdcycletime and busturnaround completion. behavior of io direction signal does depend on kind of successive read/write accesses performed to memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. io dir behavior is automatically handled by gpmc controller. for a full description of the gpmc_io_dir feature, see the omap35x technical reference manual (trm) [literature number spruf98 ]. submit documentation feedback timing requirements and switching characteristics 159 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-2. gpmc/nor flash ? synchronous single read ? (gpmcfclkdivider = 0) 160 timing requirements and switching characteristics submit documentation feedback product preview gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address d 0 out out in out f0 f12 f13 f4f6 f2 f8 f3f7 f9 f11 f1 f1 f8 f19 f18 f20 f10 f6 f19 030-021 f23 f24
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-3. gpmc/nor flash ? synchronous burst read ? 4x16-bit (gpmcfclkdivider = 0) submit documentation feedback timing requirements and switching characteristics 161 product preview gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address d 0 d 1 d 2 d 3 out out in out f0 f12 f13 f13 f12 f4 f1 f1 f2 f6 f3 f7 f8 f8 f9 f10 f11 f21 f22 f6 f7 030-022 f23 f24
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-4. gpmc/nor flash ? synchronous burst write ? (gpmcfclkdivider = 0) 162 timing requirements and switching characteristics submit documentation feedback product preview gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address d 0 d 1 d 2 d 3 out f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f14 f14 f3 f17 f17 f17 f9 f6 f17 f17 f17 030-023
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-5. gpmc/multiplexed nor flash ? synchronous burst read submit documentation feedback timing requirements and switching characteristics 163 product preview gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_a[26:17] gpmc_a[16:1]_d[15:0] gpmc_nadv_ale gpmc_noe gpmc_waitx gpmc_io_dir valid valid address (msb) address (lsb) d0 d1 d2 d3 out out in out f4 f6f4 f2 f8 f8 f10 f13 f12 f12 f11 f9 f7 f3 f0 f1 f1 f5 f6 f7 030-024 f23 f24
6.4.1.2 gpmc/nor flash interface asynchronous timing omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-6. gpmc/multiplexed nor flash ? synchronous burst write table 6-7 and table 6-8 assume testing over the recommended operating conditions (see figure 6-7 through figure 6-12 ) and electrical characteristic conditions. table 6-5. gpmc/nor flash asynchronous mode timing conditions timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance 15.94 pf table 6-6. gpmc/nor flash interface asynchronous timing ? internal parameters (1) (2) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max fi1 maximum output data generation delay from internal 6.5 9.1 13.7 ns functional clock fi2 maximum input data capture delay by internal 4 5.6 8.1 ns functional clock fi3 maximum device select generation delay from internal 6.5 9.1 13.7 ns functional clock (1) the internal parameters table must be used to calculate data access time stored in the corresponding cs register bit field. (2) internal parameters are referred to the gpmc functional internal clock which is not provided externally. timing requirements and switching characteristics 164 submit documentation feedback product preview gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir address (msb) address (lsb) d 0 d 1 d 2 d 3 out f4 f15 f15 f15 f1 f1 f2 f6 f8 f8 f0 f3 f17 f17 f17 f9 f6 f17 f17 f17 f14 f14 030-025
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-6. gpmc/nor flash interface asynchronous timing ? internal parameters (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max fi4 maximum address generation delay from internal 6.5 9.1 13.7 ns functional clock fi5 maximum address valid generation delay from internal 6.5 9.1 13.7 ns functional clock fi6 maximum byte enable generation delay from internal 6.5 9.1 13.7 ns functional clock fi7 maximum output enable generation delay from internal 6.5 9.1 13.7 ns functional clock fi8 maximum write enable generation delay from internal 6.5 9.1 13.7 ns functional clock fi9 maximum functional clock skew 100 170 200 ps table 6-7. gpmc/nor flash interface timing requirements ? asynchronous mode no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max fa5 (1) t acc(dat) data maximum access h (2) h (2) h (2) gpmc_fclk cycles time fa20 (3) t acc1-pgmode(dat) page mode successive p (4) p (4) p (4) gpmc_fclk cycles data maximum access time fa21 (5) t acc2-pgmode(dat) page mode first data h (2) h (2) h (2) gpmc_fclk cycles maximum access time (1) the fa5 parameter illustrates the amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data is internally sampled by active functional clock edge. fa5 value must be stored inside the accesstime register bit field. (2) h = accesstime * (timeparagranularity + 1) (3) the fa20 parameter illustrates amount of time required to internally sample successive input page data. it is expressed in number of gpmc functional clock cycles. after each access to input page data, next input page data is internally sampled by active functional clock edge after fa20 functional clock cycles. the fa20 value must be stored in the pageburstaccesstime register bit field. (4) p = pageburstaccesstime * (timeparagranularity + 1) (5) the fa21 parameter illustrates amount of time required to internally sample first input page data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa21 functional clock cycles, first input page data is internally sampled by active functional clock edge. fa21 value must be stored inside the accesstime register bit field. table 6-8. gpmc/nor flash interface switching characteristics ? asynchronous mode no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max t r(do) rise time, output data 2.0 2.0 2.0 ns t f(do) fall time, output data 2.0 2.0 2.0 ns fa0 t w(nbev) pulse duration, read n (12) n (12) n (12) ns gpmc_nbe0_cl write n (12) n (12) n (12) ns e, gpmc_nbe1 valid time fa1 t w(ncsv) pulse duration, read a (1) a (1) a (1) ns gpmc_ncsx (13) write a (1) a (1) a (1) ns v low fa3 t d(ncsv-nadviv) delay time, read b (2) ? 0.2 b (2) + 2.0 b (2) ? 0.2 b (2) + 2.6 b (2) ? 0.2 b (2) + 3.7 ns gpmc_ncsx (13) write b (2) ? 0.2 b (2) + 2.0 b (2) ? 0.2 b (2) + 2.6 b (2) ? 0.2 b (2) + 3.7 ns valid to gpmc_nadv_al e invalid fa4 t d(ncsv-noeiv) delay time, c (3) ? 0.2 c (3) + 2.0 c (3) ? 0.2 c (3) + 2.6 c (3) ? 0.2 c (3) + 3.7 ns gpmc_ncsx (13) valid to gpmc_noe invalid (single read) submit documentation feedback timing requirements and switching characteristics 165 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-8. gpmc/nor flash interface switching characteristics ? asynchronous mode (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max fa9 t d(av-ncsv) delay time, address j (9) ? 0.2 j (9) + 2.0 j (9) ? 0.2 j (9) + 2.6 j (9) ? 0.2 j (9) + 3.7 ns bus valid to gpmc_ncsx (13) valid fa10 t d(nbev-ncsv) delay time, j (9) ? 0.2 j (9) + 2.0 j (9) ? 0.2 j (9) + 2.6 j (9) ? 0.2 j (9) + 3.7 ns gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_ncsx (13) valid fa12 t d(ncsv-nadvv) delay time, k (10) ? 0.2 k (10) + 2.0 k (10) ? 0.2 k (10) + 2.6 k (10) ? 0.2 k (10) + 3.7 ns gpmc_ncsx (13) valid to gpmc_nadv_ale valid fa13 t d(ncsv-noev) delay time, l (11) ? 0.2 l (11) + 2.0 l (11) ? 0.2 l (11) + 2.6 l (11) ? 0.2 l (11) + 3.7 ns gpmc_ncsx (13) valid to gpmc_noe valid fa14 t d(ncsv-iodir) delay time, l (11) ? 0.2 l (11) + 2.0 l (11) ? 0.2 l (11) + 2.6 l (11) ? 0.2 l (11) + 3.7 ns gpmc_ncsx (13) valid to gpmc_io_dir high fa15 t d(ncsv-iodir) delay time, m (14) ? 0.2 m (14) + 2.0 m (14) ? 0.2 m (14) + 2.6 m (14) ? 0.2 m (14) + 3.7 ns gpmc_ncsx (13) valid to gpmc_io_dir low fa16 t w(aiv) address invalid g (7) g (7) g (7) ns duration between 2 successive r/w accesses fa18 t d(ncsv-noeiv) delay time, i (8) ? 0.2 i (8) + 2.0 i (8) ? 0.2 i (8) + 2.6 i (8) ? 0.2 i (8) + 3.7 ns gpmc_ncsx (13) valid to gpmc_noe invalid (burst read) fa20 t w(av) pulse duration, address d (4) d (4) d (4) ns valid ? 2nd, 3rd, and 4th accesses fa25 t d(ncsv-nwev) delay time, e (5) ? 0.2 e (5) + 2.0 e (5) ? 0.2 e (5) + 2.6 e (5) ? 0.2 e (5) + 3.7 ns gpmc_ncsx (13) valid to gpmc_nwe valid fa27 t d(ncsv-nweiv) delay time, f (6) ? 0.2 f (6) + 2.0 f (6) ? 0.2 f (6) + 2.6 f (6) ? 0.2 f (6) + 3.7 ns gpmc_ncsx (13) valid to gpmc_nwe invalid fa28 t d(nwev-dv) delay time, gpmc_ new 2.0 2.6 3.7 ns valid to data bus valid fa29 t d(dv-ncsv) delay time, data bus j (9) ? 0.2 j (9) + 2.0 j (9) ? 0.2 j (9) + 2.6 j (9) ? 0.2 j (9) + 3.7 ns valid to gpmc_ncsx (13) valid fa37 t d(noev-aiv) delay time, gpmc_noe 2.0 2.6 3.7 ns valid to gpmc_a[16:1]_d[15:0] address phase end (1) for single read: a = (csrdofftime ? csontime) * (timeparagranularity + 1) * gpmc_fclk for single write: a = (cswrofftime ? csontime) * (timeparagranularity + 1) * gpmc_fclk for burst read: a = (csrdofftime ? csontime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk for burst write: a = (cswrofftime ? csontime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk with n being the page burst access number (2) for reading: b = ((advrdofftime ? csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay ? csextradelay)) * gpmc_fclk for writing: b = ((advwrofftime ? csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay ? csextradelay)) * gpmc_fclk (3) c = ((oeofftime ? csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay ? csextradelay)) * gpmc_fclk (4) d = pageburstaccesstime * (timeparagranularity + 1) * gpmc_fclk (5) e = ((weontime ? csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay ? csextradelay)) * gpmc_fclk (6) f = ((weofftime ? csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay ? csextradelay)) * gpmc_fclk (7) g = cycle2cycledelay * gpmc_fclk (8) i = ((oeofftime + (n ? 1) * pageburstaccesstime ? csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay ? csextradelay)) * gpmc_fclk timing requirements and switching characteristics 166 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 (9) j = (csontime * (timeparagranularity + 1) + 0.5 * csextradelay) * gpmc_fclk (10) k = ((advontime ? csontime) * (timeparagranularity + 1) + 0.5 * (advextradelay ? csextradelay)) * gpmc_fclk (11) l = ((oeontime ? csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay ? csextradelay)) * gpmc_fclk (12) for single read: n = rdcycletime * (timeparagranularity + 1) * gpmc_fclk for single write: n = wrcycletime * (timeparagranularity + 1) * gpmc_fclk for burst read: n = (rdcycletime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk for burst write: n = (wrcycletime + (n ? 1) * pageburstaccesstime) * (timeparagranularity + 1) * gpmc_fclk (13) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (14) m = ((rdcycletime - csontime) * (timeparagranularity + 1) - 0.5 * csextradelay) * gpmc_fclk above m parameter expression is given as one example of gpmc programming. io dir signal will go from in to out after both rdcycletime and busturnaround completion. behavior of io direction signal does depend on kind of successive read/write accesses performed to memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. io dir behavior is automatically handled by gpmc controller. for a full description of the gpmc_io_dir feature, see the omap35x technical reference manual (trm) [literature number spruf98 ]. figure 6-7. gpmc/nor flash ? asynchronous read ? single word timing (1) (2) (3) (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data is internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bit field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. submit documentation feedback timing requirements and switching characteristics 167 product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address valid valid data in 0 data in 0 out out in out fa0 fa9 fa10 fa3 fa1 fa4 fa12 fa13 fa0 fa10 fa5 030-026 fa15 fa14
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-8. gpmc/nor flash ? asynchronous read ? 32-bit timing (1) (2) (3) (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data is internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bit field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. 168 timing requirements and switching characteristics submit documentation feedback product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir address 0 address 1 valid valid valid valid data upper out out in out in fa9 fa10 fa3 fa9 fa3 fa13 fa13 fa1 fa1 fa4 fa4 fa12 fa12 fa10 fa0 fa0 fa16 fa0 fa0 fa10 fa10 fa5 fa5 030-027 fa15 fa15 fa14 fa14
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-9. gpmc/nor flash ? asynchronous read ? page mode 4x16-bit timing (1) (2) (3) (4) (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa21 parameter illustrates amount of time required to internally sample first input page data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa21 functional clock cycles, first input page data is internally sampled by active functional clock edge. fa21 value must be stored inside accesstime register bit field. (3) fa20 parameter illustrates amount of time required to internally sample successive input page data. it is expressed in number of gpmc functional clock cycles. after each access to input page data, next input page data is internally sampled by active functional clock edge after fa20 functional clock cycles. fa20 is also the duration of address phases for successive input page data (excluding first input page data). fa20 value must be stored in pageburstaccesstime register bit field. (4) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. submit documentation feedback timing requirements and switching characteristics 169 product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir add0 add1 add2 add3 add4 d0 d1 d2 d3 d3 out in out fa1 fa0 fa18 fa13 fa12 fa0 fa9 fa10 fa10 fa21 fa20 fa20 fa20 030-028 fa15 fa14
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-10. gpmc/nor flash ? asynchronous write ? single word timing 170 timing requirements and switching characteristics submit documentation feedback product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir valid address data out out fa0 fa1 fa10 fa3 fa25 fa29 fa9 fa12 fa27 fa0 fa10 030-029
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-11. gpmc/multiplexed nor flash ? asynchronous read ? single word timing (1) (2) (3) (1) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) fa5 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after fa5 functional clock cycles, input data is internally sampled by active functional clock edge. fa5 value must be stored inside accesstime register bit field. (3) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. submit documentation feedback timing requirements and switching characteristics 171 product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_a[16:1]_d[15:0] gpmc_io_dir gpmc_waitx address (msb) valid valid address (lsb) data in data in out in out fa0 fa9 fa10 fa3 fa13 fa29 fa1 fa37 fa12 fa4 fa10 fa0 fa5 030-030 fa15 fa14
6.4.1.3 gpmc/nand flash interface timing omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0, 1, 2, or 3. figure 6-12. gpmc/multiplexed nor flash ? asynchronous write ? single word timing table 6-10 through table 6-12 assume testing over the recommended operating conditions (see figure 6-13 through figure 6-16 ) and electrical characteristic conditions. table 6-9. gpmc/nand flash asynchronous mode timing conditions timing condition parameter value unit input conditions t r input signal rise time 1.8 ns t f input signal fall time 1.8 ns output conditions c load output load capacitance 15.94 pf table 6-10. gpmc/nand flash interface asynchronous timing ? internal parameters (1) (2) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max gnfi1 maximum output data generation delay from 6.5 9.1 13.7 ns internal functional clock gnfi2 maximum input data capture delay by internal 4 5.6 8.1 ns functional clock (1) internal parameters table must be used to calculate data access time stored in the corresponding cs register bit field. (2) internal parameters are referred to the gpmc functional internal clock which is not provided externally. timing requirements and switching characteristics 172 submit documentation feedback product preview gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[26:17] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_a[16:1]_d[15:0] gpmc_waitx gpmc_io_dir address (msb) valid address (lsb) data out out fa0 fa1 fa9 fa10 fa3 fa25 fa29 fa12 fa27 fa28 fa0 fa10 030-031
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-10. gpmc/nand flash interface asynchronous timing ? internal parameters (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max gnfi3 maximum device select generation delay from 6.5 9.1 13.7 ns internal functional clock gnfi4 maximum address latch enable generation delay 6.5 9.1 13.7 ns from internal functional clock gnfi5 maximum command latch enable generation 6.5 9.1 13.7 ns delay from internal functional clock gnfi6 maximum output enable generation delay from 6.5 9.1 13.7 ns internal functional clock gnfi7 maximum write enable generation delay from 6.5 9.1 13.7 ns internal functional clock gnfi8 maximum functional clock skew 100 170 200 ps table 6-11. gpmc/nand flash interface timing requirements no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max gnf12 (1) t acc(dat) data maximum access time j (2) j (2) j (2) gpmc_fclk cycles (1) the gnf12 parameter illustrates the amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of the read cycle and after gnf12 functional clock cycles, input data is internally sampled by the active functional clock edge. the gnf12 value must be stored inside accesstime register bit field. (2) j = accesstime * (timeparagranularity + 1) table 6-12. gpmc/nand flash interface switching characteristics no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max t r(do) rise time, output 2.0 2.0 2.0 ns data t f(do) fall time, output 2.0 2.0 2.0 ns data gnf0 t w(nwev) pulse duration, a (1) a (1) a (1) ns gpmc_nwe valid time gnf1 t d(ncsv-nwev) delay time, b (2) ? 0.2 b (2) + 2.0 b (2) ? 0.2 b (2) + 2.6 b (2) ? 0.2 b (2) + 3.7 ns gpmc_ncsx (13) valid to gpmc_nwe valid gnf2 t w(cleh-nwev) delay time, c (3) ? 0.2 c (3) + 2.0 c (3) ? 0.2 c (3) + 2.6 c (3) ? 0.2 c (3) + 3.7 ns gpmc_nbe0_cle high to gpmc_nwe valid gnf3 t w(nwev-dv) delay time, d (4) ? 0.2 d (4) + 2.0 d (4) ? 0.2 d (4) + 2.6 d (4) ? 0.2 d (4) + 3.7 ns gpmc_d[15:0] valid to gpmc_nwe valid gnf4 t w(nweiv-div) delay time, e (5) ? 0.2 e (5) + 2.0 e (5) ? 0.2 e (5) + 2.6 e (5) ? 0.2 e (5) + 3.7 ns gpmc_nwe invalid to gpmc_d[15:0] invalid gnf5 t w(nweiv-cleiv) delay time, f (6) ? 0.2 f (6) + 2.0 f (6) ? 0.2 f (6) + 2.6 f (6) ? 0.2 f (6) + 3.7 ns gpmc_nwe invalid to gpmc_nbe0_cle invalid submit documentation feedback timing requirements and switching characteristics 173 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-12. gpmc/nand flash interface switching characteristics (continued) no. parameter 1.15 v 1.0 v 0.9 v unit min max min max min max gnf6 t w(nweiv-ncsiv) delay time, g (7) ? 0.2 g (7) + 2.0 g (7) ? 0.2 g (7) + 2.6 g (7) ? 0.2 g (7) + 3.7 ns gpmc_nwe invalid to gpmc_ncsx (13) invalid gnf7 t w(aleh-nwev) delay time, c (3) ? 0.2 c (3) + 2.0 c (3) ? 0.2 c (3) + 2.6 c (3) ? 0.2 c (3) + 3.7 ns gpmc_nadv_ale high to gpmc_nwe valid gnf8 t w(nweiv-aleiv) delay time, f (6) ? 0.2 f (6) + 2.0 f (6) ? 0.2 f (6) + 2.6 f (6) ? 0.2 f (6) + 3.7 ns gpmc_nwe invalid to gpmc_nadv_ale invalid gnf9 t c(nwe) cycle time, write h (8) h (8) h (8) ns cycle time gnf10 t d(ncsv-noev) delay time, i (9) ? 0.2 i (9) + 2.0 i (9) ? 0.2 i (9) + 2.6 i (9) ? 0.2 i (9) + 3.7 ns gpmc_ncsx (13) valid to gpmc_noe valid gnf13 t w(noev) pulse duration, k (10) k (10) k (10) ns gpmc_noe valid time gnf14 t c(noe) cycle time, read l (11) l (11) l (11) ns cycle time gnf15 t w(noeiv-ncsiv) delay time, m (12) ? 0.2 m (12) + 2.0 m (12) ? 0.2 m (12) + 2.6 m (12) ? 0.2 m (12) + 3.7 ns gpmc_noe invalid to gpmc_ncsx (13) invalid (1) a = (weofftime ? weontime) * (timeparagranularity + 1) * gpmc_fclk (2) b = ((weontime ? csontime) * (timeparagranularity + 1) + 0.5 * (weextradelay ? csextradelay)) * gpmc_fclk (3) c = ((weontime ? advontime) * (timeparagranularity + 1) + 0.5 * (weextradelay ? advextradelay)) * gpmc_fclk (4) d = (weontime * (timeparagranularity + 1) + 0.5 * weextradelay ) * gpmc_fclk (5) e = (wrcycletime ? weofftime * (timeparagranularity + 1) ? 0.5 * weextradelay ) * gpmc_fclk (6) f = (advwrofftime ? weofftime * (timeparagranularity + 1) + 0.5 * (advextradelay ? weextradelay ) * gpmc_fclk (7) g = (cswrofftime ? weofftime * (timeparagranularity + 1) + 0.5 * (csextradelay ? weextradelay ) * gpmc_fclk (8) h = wrcycletime * (1 + timeparagranularity) * gpmc_fclk (9) i = ((oeontime ? csontime) * (timeparagranularity + 1) + 0.5 * (oeextradelay ? csextradelay)) * gpmc_fclk (10) k = (oeofftime ? oeontime) * (1 + timeparagranularity) * gpmc_fclk (11) l = rdcycletime * (1 + timeparagranularity) * gpmc_fclk (12) m = (csrdofftime ? oeofftime * (timeparagranularity + 1) + 0.5 * (csextradelay ? oeextradelay ) * gpmc_fclk (13) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. 174 timing requirements and switching characteristics submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. figure 6-13. gpmc/nand flash ? command latch cycle timing in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. figure 6-14. gpmc/nand flash ? address latch cycle timing submit documentation feedback timing requirements and switching characteristics 175 product preview gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] command gnf0 gnf1 gnf2 gnf3 gnf4 gnf5 gnf6 030-032 gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] address gnf0 gnf1 gnf7 gnf3 gnf4 gnf6 gnf8 gnf9 030-033
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-15. gpmc/nand flash ? data read cycle timing (1) (2) (3) (1) the gnf12 parameter illustrates amount of time required to internally sample input data. it is expressed in number of gpmc functional clock cycles. from start of read cycle and after gnf12 functional clock cycles, input data is internally sampled by active functional clock edge. the gnf12 value must be stored inside accesstime register bit field. (2) gpmc_fclk is an internal clock (gpmc functional clock) not provided externally. (3) in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0 ,1, 2, or 3. in gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. in gpmc_waitx, x is equal to 0 or 1. figure 6-16. gpmc/nand flash ? data write cycle timing 176 timing requirements and switching characteristics submit documentation feedback product preview gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_a[16:1]_d[15:0] gpmc_waitx data gnf10 gnf13 gnf14 gnf15 gnf12 030-034 gpmc_fclk gpmc_ncsx gpmc_nbe0_clegpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1]_d[15:0] data gnf0 gnf1 gnf4 gnf6 gnf9 gnf3 030-035
6.4.2 sdram controller subsystem (sdrc) 6.4.2.1 sdram controller subsystem device-specific information 6.4.2.2 lpddr interface omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the sdram controller subsystem (sdrc) module provides connectivity between the omap35 30/2530/2530/2530/25 applications processor and external dram memory components. the sdrc module only supports low-power double-data-rate (lpddr) sdram devices. memory devices can be interfaced to the sdrc using a stacked-memory approach or through the printed circuit board (pcb). the stacked-memory approach uses the package-on-package memory interface pins (available only on cbb package). the approach to specifying interface timing for the sdrc memory bus is different than on other interfaces such as the general-purpose memory controller (gpmc) and the multi-channel buffered serial ports (mcbsps). for these other interfaces the device timing was specified in terms of data manual specifications and i/o buffer information specification (ibis) models. for the sdrc memory bus, the approach is to specify compatible memory devices and provide the printed circuit board (pcb) solution and guidelines directly to the user. texas instruments (ti) has performed the simulation and system characterization to ensure all interface timings in this solution are met. the lpddr interface is balled out on the bottom side of all omap35x packages and on the top side of omap35x pop packages. the lpddr interface on the top of the pop package has been designed for compatibility any pop lpddr device with a matching footprint and compliance with the jedec lpddr-266 specification. this section provides the timing specification for the bottom-side lpddr interface as a pcb design and manufacturing specification. the design rules constrain pcb trace length, pcb trace skew, signal integrity, cross-talk, and signal timing. these rules, when followed, result in a reliable lpddr memory system without the need for a complex timing closure process. for more information regarding guidelines for using this lpddr specification, see the understanding ti's pcb routing rule-based ddr timing specification application report (literature number spraav0 ). 6.4.2.2.1 lpddr interface schematic figure 6-17 and figure 6-18 show the lpddr interface schematics for a lpddr memory system. the 1 x16 lpddr system schematic is identical to figure 6-17 except that the high word lpddr device is deleted. submit documentation feedback timing requirements and switching characteristics 177 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-17. omap35x lpddr high level schematic (x16 memories) 178 timing requirements and switching characteristics submit documentation feedback product preview sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0sdrc_ncs1 n/c sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0sdrc_cke1 n/c sdrc_clk sdrc_nclk t t t t t t t t t t t t t t t t t t t dq0dq7 ldm ldqs dq8 dq15 udm udqs ba0 ba1 a0 a14 cs cas ras we ckeck ck ba0ba1 a0 a14 cs cas ras we ckeck ck t t t t t t t t lpddr omap35x dq0dq7 ldm ldqs dq8 dq15udm udqs lpddr
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-18. omap35x lpddr high level schematic (x32 memory) 6.4.2.2.2 compatible jedec lpddr devices table 6-13 shows the parameters of the jedec lpddr devices that are compatible with this interface. generally, the lpddr interface is compatible with x16 and x32 lpddr266 and lpddr333 speed grade lpddr devices. table 6-13. compatible jedec lpddr devices no. parameter min max unit notes jedec lpddr device speed 1 lpddr-266 see note (1) grade 2 jedec lpddr device bit width 16 32 bits 3 jedec lpddr device count 1 2 devices see note (2) jedec lpddr device ball 4 60 90 balls count (1) higher lpddr speed grades are supported due to inherent jedec lpddr backwards compatibility. (2) 1 x16 lpddr device is used for 16 bit lpddr memory system. 1x32 or 2x16 lpddr devices are used for a 32-bit lpddr memory system. submit documentation feedback timing requirements and switching characteristics 179 product preview sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk t t t t t t t t t t t t t t t t t t t ba0ba1 a0 a14 cs cas ras we ckeck ck t t t t t t t t omap35x dq0dq7 dm0 dqs0 dq8 dq15dm1 dqs1 lpddr dq16dq23 dm2 dqs2 dq24 dq31 dm3 dqs3 n/c n/c sdrc_ncs1 sdrc_cke1
6.4.2.3 placement omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com 6.4.2.2.3 pcb stackup the minimum stackup required for routing the omap35x is a six layer stack as shown in table 6-14 . additional layers may be added to the pcb stack up to accommodate other circuity or to reduce the size of the pcb footprint. table 6-14. omap35x minimum pcb stack up layer type description 1 signal top routing mostly horizontal 2 plane ground 3 plane power 4 signal internal routing 5 plane ground 6 signal bottom routing mostly vertical table 6-15. pcb stack up specifications no. parameter min typ max unit notes 1 pcb routing/plane layers 6 2 signal routing layers 3 3 full ground layers under lpddr routing region 2 4 number of ground plane cuts allowed within lpddr routing region 0 number of ground reference planes required for each lpddr routing 1 5 1 layer number of layers between lpddr routing layer and reference ground 0 6 0 plane 7 pcb routing feature size 4 mils 8 pcb trace width w 4 mils 9 pcb bga escape via pad size 18 mils 10 pcb bga escape via hole size 8 mils 11 device bga pad size see note (1) 12 lpddr device bga pad size see note (2) 13 single ended impedance, zo 50 75 w 14 impedance control z-5 z z + 5 w see note (3) (1) please see the flip chip ball grid array package reference guide (literature number spru811 ) for device bga pad size. (2) please see the lpddr device manufacturer documentation for the lpddr device bga pad size. (3) z is the nominal singled ended impedance selected for the pcb specified by item 12. figure 6-19 shows the required placement for the omap35x device as well as the lpddr devices. the dimensions for figure 6-19 are defined in table 6-16 . the placement does not restrict the side of the pcb that the devices are mounted on. the ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. for 1x16 and 1x32 lpddr memory systems, the second lpddr device is omitted from the placement. 180 timing requirements and switching characteristics submit documentation feedback product preview
6.4.2.4 lpddr keep out region omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-19. omap35x and lpddr device placement table 6-16. placement specifications no. parameter min max unit notes 1 x 1440 mils see notes (1) , (2) 2 y 1030 mils see notes (1) , (2) 3 y offset 525 mils see notes (1) , (2) , (3) 4 lpddr keepout region see note (4) clearance from non-lpddr signal to lpddr 5 4 w see note (5) keepout region (1) see figure 6-17 for dimension definitions. (2) measurements from center of device to center of lpddr device. (3) for 16 bit memory systems it is recommended that y offset be as small as possible. (4) lpddr keepout region to encompass entire lpddr routing area. (5) non-lpddr signals allowed within lpddr keepout region provided they are separated from lpddr routing layers by a ground plane. the region of the pcb used for the lpddr circuitry must be isolated from other signals. the lpddr keep out region is defined for this purpose and is shown in figure 6-20 . the size of this region varies with the placement and lpddr routing. additional clearances required for the keep out region are shown in table 6-16 . submit documentation feedback timing requirements and switching characteristics 181 product preview a1a1 x y offset recommended lpddr device orientation y y offset lpddr device lpddr controller omap
6.4.2.5 net classes 6.4.2.6 lpddr signal termination omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-20. lpddr keepout region table 6-17 lists the clock net classes for the lpddr interface. table 6-18 lists the signal net classes, and associated clock net classes, for the signals in the lpddr interface. these net classes are used for the termination and routing rules that follow. table 6-17. clock net class definitions clock net class omap pin names ck sdrc_clk/sdrc_nclk dqs0 sdrc_dqs0 dqs1 sdrc_dqs1 dqs2 sdrc_dqs2 dqs3 sdrc_dqs3 table 6-18. signal net class definitions clock net class associated clock net class omap pin names sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas, addr_ctrl ck sdrc_nras, sdrc_nwe, sdrc_cke0 dq0 dqs0 sdrc_d, sdrc_dm0 dq1 dqs1 sdrc_d, sdrc_dm1 dq2 dqs2 sdrc_d, sdrc_dm2 dq3 dqs3 sdrc_d, sdrc_dm3 no terminations of any kind are required in order to meet signal integrity and overshoot requirements. serial terminators are permitted, if desired, to reduce emi risk; however, serial terminations are the only type permitted. table 6-19 shows the specifications for the series terminators. table 6-19. lpddr signal terminations no. parameter min typ max unit notes 1 ck net class 0 10 w see note (1) (1) only series termination is permitted, parallel or sst specifically disallowed. timing requirements and switching characteristics 182 submit documentation feedback product preview a1a1 lpddr controller lpddr device region should encompass all lpddr circuitry and varies dependingon placement. non-lpddr signals should not be routed on the lpddr signal layers within the lpddr keep out region. non-lpddr signals may be routed in the region provided they are routed on layers separated from lpddr signal layers by a ground layer. no breaks should be allowed in the reference ground layers in this region. in addition, the 1.8 v power plane should cover the entire keep out region.
6.4.2.7 lpddr ck and addr_ctrl routing omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-19. lpddr signal terminations (continued) no. parameter min typ max unit notes 2 addr_ctrl net class 0 22 zo w see notes (1) , (2) , (3) data byte net classes 3 0 22 zo w see notes (1) , (2) , (3) (dqs0-dqs3, dq0-dq3) (2) terminator values larger than typical only recommended to address emi issues. (3) termination value should be uniform across net class. figure 6-21 shows the topology of the routing for the ck and addr_ctrl net classes. the route is a balanced t as it is intended that the length of segments b and c be equal. in addition, the length of a should be maximized. figure 6-21. ck and addr_ctrl routing and topology table 6-20. ck and addr_ctrl routing specification no. parameter min typ max unit notes 1 center to center ck-ck spacing 2w 2 ck a to b/a to c skew length mismatch 25 mils see note (1) 3 ck b to c skew length mismatch 25 mils center to center ck to other 4 4w see note (2) lpddr trace spacing 5 ck/addr_ctrl nominal trace length caclm-50 caclm caclm+50 mils see note (3) 6 addr_ctrl to ck skew length mismatch 100 mils addr_ctrl to addr_ctrl 7 100 mils skew length mismatch center to center addr_ctrl to other 8 4w see note (2) lpddr trace 4w spacing center to center addr_ctrl to other 9 3w see note (2) addr_ctrl 3w trace spacing addr_ctrl a to b/a to c skew length 10 100 mils see note (1) mismatch 11 addr_ctrl b to c skew length mismatch 100 mils (1) series terminator, if used, should be located closest to device. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) caclm is the longest manhattan distance of the ck and addr_ctrl net classes. submit documentation feedback timing requirements and switching characteristics 183 product preview a1 a1 c b a t lpddr controller omap
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-22 shows the topology and routing for the dqs and dq net classes; the routes are point to point. skew matching across bytes is not needed nor recommended. figure 6-22. dqs and dq routing and topology table 6-21. dqs and dq routing specification (1) no. parameter min typ max unit notes 2 dqs e skew length mismatch 25 mils center to center dqs to other lpddr 3 4w see note (2) trace spacing 4 dqs/dq nominal trace length dqlm - 50 dqlm dqlm + 50 mils see note (3) 5 dq to dqs skew length mismatch 100 mils 6 dq to dq skew length mismatch 100 mils center to center dq to other lpddr 7 4w see note (2) trace spacing center to center dq to other dq trace 8 3w see note (2) , (4) spacing 9 dq e skew length mismatch 100 mils (1) series terminator, if used, should be located closest to lpddr. (2) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (3) center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate bga escape and routing congestion. (4) dqlm is the longest manhattan distance of the dqs and dq net classes. timing requirements and switching characteristics 184 submit documentation feedback product preview a1 a1 e0 t e1 t e2 omap e3 t lpddr controller t
6.5 video interfaces 6.5.1 camera interface 6.5.1.1 parallel camera interface timing omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the camera subsystem provides the system interfaces and the processing capability to connect raw, yuv, or jpeg image sensor modules to the omap35 15/03 device for video-preview, video-record, and still-image-capture applications. the camera subsystem supports up to two simultaneous pixel flows but only one of them can use the video processing hardware: parallel : the parallel interface data must go through the video processing hardware. the parallel camera interface is a 12-bit interface which can be used in two modes: 1. sync mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. the pixel clock can be up to 75 mhz in 12-bit mode. the pixel clock can be up to 130 mhz in 8-bit packed mode. 2. itu mode provides an itu-r bt 656 compatible data stream with progressive image sensor modules only in 8- and 10-bit configurations. the pixel clock can be up to 75 mhz. 6.5.1.1.1 sync normal mode 6.5.1.1.1.1 12-bit sync normal ? progressive mode table 6-23 and table 6-24 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-23 ). table 6-22. isp timing conditions ? 12-bit sync normal ? progressive mode timing condition parameter value unit input conditions t r input signal rise time 2.7 ns t f input signal fall time 2.7 ns output condition c load output load capacitance 8.6 pf table 6-23. isp timing requirements ? 12-bit sync normal ? progressive mode (1) no. parameter 1.15 v 1.0 v unit min max min max isp17 t c(pclk) cycle time (2) , cam_pclk period 13.3 22.2 ns isp18 t w(pclkh) typical pulse duration, cam_pclk high 0.5*p (3) 0.5*p (3) ns isp18 t w(pclkl) typical pulse duration, cam_pclk low 0.5*p (3) 0.5*p (3) ns t dc(pclk) duty cycle error, cam_pclk 667 1111 ps t j(pclk) cycle jitter (4) , cam_pclk 133 200 ps isp19 t su(dv-pclkh) setup time, cam_d[11:0] valid before cam_pclk rising 1.82 3.25 ns edge isp20 t h(pclkh-dv) hold time, cam_d[11:0] valid after cam_pclk rising 1.82 3.25 ns edge isp21 t su(dv-vsh) setup time, cam_vs valid before cam_pclk rising 1.82 3.25 ns edge isp22 t h(pclkh-vsv) hold time, cam_vs valid after cam_pclk rising edge 1.82 3.25 ns isp23 t su(dv-hsh) setup time, cam_hs valid before cam_pclk rising 1.82 3.25 ns edge (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the isp module. (3) p = cam_pclk period in ns (4) maximum cycle jitter supported by cam_pclk input clock. submit documentation feedback timing requirements and switching characteristics 185 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-23. isp timing requirements ? 12-bit sync normal ? progressive mode (continued) no. parameter 1.15 v 1.0 v unit min max min max isp24 t h(pclkh-hsv) hold time, cam_hs valid after cam_pclk rising edge 1.82 3.25 ns isp25 t su(dv-hsh) setup time, cam_wen valid before cam_pclk rising 1.82 3.25 ns edge isp26 t h(pclkh-hsv) hold time, cam_wen valid after cam_pclk rising edge 1.82 3.25 ns table 6-24. isp switching characteristics ? 12-bit sync normal ? progressive mode no. parameter 1.15 v 1.0 v unit min max min max isp15 t c(xclk) cycle time (1) , cam_xclk period 4.6 4.6 ns isp16 t w(xclkh) typical pulse duration, cam_xclk high 0.5*po (2) 0.5*po (2) ns isp16 t w(xclkl) typical pulse duration, cam_xclk low 0.5*po (2) 0.5*po (2) ns t dc(xclk) duty cycle error, cam_xclk 231 231 ps t j(xclk) jitter standard deviation (3) , cam_xclk 33 33 ps t r(xclk) rise time, cam_xclk 0.93 0.93 ns t f(xclk) fall time, cam_xclk 0.93 0.93 ns (1) related with the cam_xclk maximum and minimum frequencies programmable in the isp module. warning: the camera sensor or the camera module must be disabled to change the frequency configuration. for more information, see the omap35x technical reference manual (trm) [literature number spruf98 ] (2) po = cam_xclk period in ns (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 186 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-23. isp ? 12-bit sync normal ? progressive mode (1) (2) (3) (4) (5) (6) (7) (8) (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. if the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) the parallel camera in sync mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) when the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded. (4) however, it is possible to shift the data to 0, 2, or 4 data internal lanes. (5) the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode, and cam_d[11:0] in 12-bit mode. (6) optionally, the data write to memory can be qualified by the external cam_wen signal. (7) the cam_wen signal can be used as a external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) in cam_xclki; i is equal to a or b. 6.5.1.1.1.2 8-bit packed sync ? progressive mode table 6-26 and table 6-27 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-24 ). table 6-25. isp timing conditions ? 8-bit packed sync ? progressive mode timing condition parameter value unit input conditions t r input signal rise time 2.5 ns t f input signal fall time 2.5 ns output conditions submit documentation feedback timing requirements and switching characteristics 187 product preview cam_xclki cam_pclk cam_vs cam_hs cam_d[11:0] cam_wen cam_fld d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(n-1) isp15 isp16 isp16 isp17 isp18 isp19 isp20 isp21 isp22 isp24 isp23 isp25 isp26 isp18 030-056
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-25. isp timing conditions ? 8-bit packed sync ? progressive mode (continued) timing condition parameter value unit c load output load capacitance 8.6 pf table 6-26. isp timing requirements ? 8-bit packed sync ? progressive mode (1) no. parameter 1.15 v 1.0 v unit min max min max isp3 t c(pclk) cycle time (2) , cam_pclk period 7.7 15.4 ns isp4 t w(pclkh) typical pulse duration, cam_pclk high 0.5*p (3) 0.5*p (3) ns isp4 t w(pclkl) typical pulse duration, cam_pclk low 0.5*p (3) 0.5*p (3) ns t dc(pclk) duty cycle error, cam_pclk 385 769 ps t j(pclk) cycle jitter (4) , cam_pclk 83 167 ps isp5 t su(dv-pclkh) setup time, cam_d[11:0] valid before cam_pclk 1.08 2.27 ns rising edge isp6 t h(pclkh-dv) hold time, cam_d[11:0] valid after cam_pclk rising 1.08 2.27 ns edge isp7 t su(dv-vsh) setup time, cam_vs valid before cam_pclk rising 1.08 2.27 ns edge isp8 t h(pclkh-vsv) hold time, cam_vs valid after cam_pclk rising edge 1.08 2.27 ns isp9 t su(dv-hsh) setup time, cam_hs valid before cam_pclk rising 1.08 2.27 ns edge isp10 t h(pclkh-hsv) hold time, cam_hs valid after cam_pclk rising edge 1.08 2.27 ns isp11 t su(dv-hsh) setup time, cam_wen valid before cam_pclk rising 1.08 2.27 ns edge isp12 t h(pclkh-hsv) hold time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the isp module. (3) p = cam_pclk period in ns. (4) maximum cycle jitter supported by cam_pclk input clock. table 6-27. isp switching characteristics ? 8-bit packed sync ? progressive mode no. parameter 1.15 v 1.0 v unit min max min max isp1 t c(xclk) cycle time (1) , cam_xclk period 4.6 4.6 ns isp2 t w(xclkh) typical pulse duration, cam_xclk high 0.5*po (2) 0.5*po (2) ns isp2 t w(xclkl) typical pulse duration, cam_xclk low 0.5*po (2) 0.5*po (2) ns t dc(xclk) duty cycle error, cam_xclk 231 231 ps t j(xclk) jitter standard deviation (3) , cam_xclk 67 67 ps t r(xclk) rise time, cam_xclk 0.93 0.93 ns t f(xclk) fall time, cam_xclk 0.93 0.93 ns (1) related with the cam_xclk maximum and minimum frequencies programmable in the isp module. warning: you must disable the camera sensor or the camera module to change the frequency configuration. for more information, see the omap35x technical reference manual (trm) [literature number spruf98 (2) po = cam_xclk period in ns (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 188 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-24. isp ? 8-bit packed sync ? progressive mode (1) (2) (3) (4) (5) (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) the image sensor must be connected to the lower data lines and the unused lines must be grounded. however, it is possible to shift the data to 0, 2, or 4 data internal lanes. the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode. (3) optionally, the data write to memory can be qualified by the external cam_wen signal. the cam_wen signal can be used as a external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. the polarity of cam_fld is programmable. (4) the camera module can pack 8-bit data into 16 bits. it doubles the maximum pixel clock. this mode can be particularly useful to transfer a ycbcr data stream or compressed stream to memory at very high speed. (5) in cam_xclki; i is equal to a or b. 6.5.1.1.1.3 12-bit sync normal ? interlaced mode table 6-29 and table 6-30 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-25 ). table 6-28. isp timing conditions ? 12-bit sync normal ? interlaced mode timing condition parameter value unit input conditions t r input signal rise time 2.7 ns t f input signal fall time 2.7 ns output conditions submit documentation feedback timing requirements and switching characteristics 189 product preview cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(n-1) isp1 isp2 isp2 isp3 isp4 isp5 isp6 isp7 isp8 isp10 isp4 isp9 isp11 030-059 isp12
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-28. isp timing conditions ? 12-bit sync normal ? interlaced mode (continued) timing condition parameter value unit c load output load capacitance 8.6 pf table 6-29. isp timing requirements ? 12-bit sync normal ? interlaced mode (1) no. parameter 1.15 v 1.0 v unit min max min max isp17 t c(pclk) cycle time (2) , cam_pclk period 13.3 22.2 ns isp18 t w(pclkh) typical pulse duration, cam_pclk high 0.5*p (3) 0.5*p (3) ns isp18 t w(pclkl) typical pulse duration, cam_pclk low 0.5*p (3) 0.5*p (3) ns t dc(pclk) duty cycle error, cam_pclk 667 1111 ps t j(pclk) cycle jitter (4) , cam_pclk 133 200 ps isp19 t su(dv-pclkh) setup time, cam_d[11:0] valid before cam_pclk 1.82 3.25 ns rising edge isp20 t h(pclkh-dv) hold time, cam_d[11:0] valid after cam_pclk rising 1.82 3.25 ns edge isp21 t su(dv-vsh) setup time, cam_vs valid before cam_pclk rising 1.82 3.25 ns edge isp22 t h(pclkh-vsv) hold time, cam_vs valid after cam_pclk rising edge 1.82 3.25 ns isp23 t su(dv-hsh) setup time, cam_hs valid before cam_pclk rising 1.82 3.25 ns edge isp24 t h(pclkh-hsv) hold time, cam_hs valid after cam_pclk rising edge 1.82 3.25 ns isp25 t su(dv-hsh) setup time, cam_wen valid before cam_pclk rising 1.82 3.25 ns edge isp26 t h(pclkh-hsv) hold time, cam_wen valid after cam_pclk rising 1.82 3.25 ns edge isp27 t su(dv-fldh) setup time, cam_fld valid before cam_pclk rising 1.82 3.25 ns edge isp28 t h(pclkh-fldv) hold time, cam_fld valid after cam_pclk rising edge 1.82 3.25 ns (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the isp module. (3) p = cam_lclk period in ns. (4) maximum cycle jitter supported by cam_pclk input clock. table 6-30. isp switching characteristics ? 12-bit sync normal ? interlaced mode no. parameter 1.15 v 1.0 v unit min max min max isp15 t c(xclk) cycle time (1) , cam_xclk period 4.6 4.6 ns isp16 t w(xclkh) typical pulse duration, cam_xclk high 0.5*po (2) 0.5*po (2) ns isp16 t w(xclkl) typical pulse duration, cam_xclk low 0.5*po (2) 0.5*po (2) ns t dc(xclk) duty cycle error, cam_xclk 231 231 ps t j(xclk) jitter standard deviation (3) , cam_xclk 33 33 ps t r(xclk) rise time, cam_xclk 0.93 0.93 ns t f(xclk) fall time, cam_xclk 0.93 0.93 ns (1) related with the cam_xclk maximum and minimum frequencies programmable in the isp module. warning: you must disable the camera sensor or the camera module to change the frequency configuration. for more information, see the omap35x technical reference manual (trm) [literature number spruf98 (2) po = cam_xclk period in ns. (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 190 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-25. isp ? 12-bit sync normal ? interlaced mode (1) (2) (3) (4) (5) (6) (7) (8) (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. if the cam_hs, cam_vs, and cam_fld signals are output, the signal length can be set. (2) the parallel camera in sync mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data. (3) when the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be grounded. (4) it is possible to shift the data to 0, 2, or 4 data internal lanes. (5) the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit mode, and cam_d[11:0] in 12-bit mode. (6) optionally, the data write to memory can be qualified by the external cam_wen signal. (7) the cam_wen signal can be used as a external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (8) in cam_xclki; i is equal to a or b. 6.5.1.1.1.4 8-bit packed sync ? interlaced mode table 6-32 and table 6-33 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-26 ). submit documentation feedback timing requirements and switching characteristics 191 product preview cam_xclki cam_pclk cam_vs cam_hs cam_d[11:0] cam_wen cam_fld frame(0) frame(0) l(0) l(n-1) l(0) d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(2) d(n-1) pair impair isp15 isp16 isp16 isp17 isp18 isp18 isp27 isp19 isp21 isp22 isp23 isp20 isp28 isp24 isp25 isp26 030-057
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-31. isp timing conditions ? 8-bit packed sync ? interlaced mode timing condition parameter value unit input conditions t r input signal rise time 2.5 ns t f input signal fall time 2.5 ns output conditions c load output load capacitance 8.6 pf table 6-32. isp timing requirements ? 8-bit packed sync ? interlaced mode (1) no. parameter 1.15 v 1.0 v unit min max min max isp3 t c(pclk) cycle time (2) , cam_pclk period 7.7 15.4 ns isp4 t w(pclkh) typical pulse duration, cam_pclk high 0.5*p (3) 0.5*p (3) ns isp4 t w(pclkl) typical pulse duration, cam_pclk low 0.5*p (3) 0.5*p (3) ns t dc(pclk) duty cycle error, cam_pclk 385 769 ps t j(pclk) cycle jitter (4) , cam_pclk 83 167 ps isp5 t su(dv-pclkh) setup time, cam_d[11:0] valid before cam_pclk 1.08 2.27 ns rising edge isp6 t h(pclkh-dv) hold time, cam_d[11:0] valid after cam_pclk rising 1.08 2.27 ns edge isp7 t su(dv-vsh) setup time, cam_vs valid before cam_pclk rising 1.08 2.27 ns edge isp8 t h(pclkh-vsv) hold time, cam_vs valid after cam_pclk rising edge 1.08 2.27 ns isp9 t su(dv-hsh) setup time, cam_hs valid before cam_pclk rising 1.08 2.27 ns edge isp10 t h(pclkh-hsv) hold time, cam_hs valid after cam_pclk rising edge 1.08 2.27 ns isp11 t su(dv-hsh) setup time, cam_wen valid before cam_pclk rising 1.08 2.27 ns edge isp12 t h(pclkh-hsv) hold time, cam_wen valid after cam_pclk rising edge 1.08 2.27 ns isp13 t su(dv-fldh) setup time, cam_fld valid before cam_pclk rising 1.08 2.27 ns edge isp14 t h(pclkh-fldv) hold time, cam_fld valid after cam_pclk rising edge 1.08 2.27 ns (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the isp module. (3) p = cam_lclk period in ns. (4) maximum cycle jitter supported by cam_pclk input clock. table 6-33. isp switching characteristics ? 8-bit packed sync ? interlaced mode no. parameter 1.15 v 1.0 v unit min max min max isp16 t c(xclk) cycle time (1) , cam_xclk period 4.6 4.6 ns isp2 t w(xclkh) typical pulse duration, cam_xclk high 0.5*po (2) 0.5*po (2) ns isp2 t w(xclkl) typical pulse duration, cam_xclk low 0.5*po (2) 0.5*po (2) ns t dc(xclk) duty cycle error, cam_xclk 231 231 ps t j(xclk) jitter standard deviation (3) , cam_xclk 67 67 ps t r(xclk) rise time, cam_xclk 0.93 0.93 ns t f(xclk) fall time, cam_xclk 0.93 0.93 ns (1) related with the cam_xclk maximum and minimum frequencies programmable in the isp module. warning: you must disable the camera sensor or the camera module to change the frequency configuration. for more information, see the omap35x technical reference manual (trm) [literature number spruf98 (2) po = cam_xclk period in ns. (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 192 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-26. isp ? 8-bit packed sync ? interlaced mode (1) (2) (3) (4) (5) (1) the polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. (2) the image sensor must be connected to the lower data lines and the unused lines must be grounded. however, it is possible to shift the data to 0, 2, or 4 data internal lanes. the bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode. (3) optionally, the data write to memory can be qualified by the external cam_wen signal. the cam_wen signal can be used as a external memory write-enable signal. the data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. (4) the camera module can pack 8-bit data into 16 bits. it doubles the maximum pixel clock. this mode can be particularly useful to transfer a ycbcr data stream or compressed stream to memory at very high speed. (5) in cam_xclki; i is equal to a or b. 6.5.1.1.2 itu mode table 6-35 and table 6-36 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-27 ). table 6-34. isp timing conditions ? itu mode timing condition parameter value unit input conditions t r input signal rise time 2.7 ns submit documentation feedback timing requirements and switching characteristics 193 product preview cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld frame(0) frame(0) l(0) l(n-1) l(0) d(0) d(n-3) d(n-2) d(n-1) d(0) d(1) d(2) d(n-1) pair impair isp1 isp2 isp2 isp3 isp4 isp4 isp13 isp5isp7 isp8 isp9 isp6isp14 isp10 isp11 isp12 030-060
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-34. isp timing conditions ? itu mode (continued) timing condition parameter value unit t f input signal fall time 2.7 ns output conditions c load output load capacitance 8.6 pf table 6-35. isp timing requirements ? itu mode (1) no. parameter 1.15 v 1.0 v unit min max min max isp17 t c(pclk) cycle time (2) , cam_pclk period 13.3 22.2 ns isp18 t w(pclkh) typical pulse duration, cam_pclk high 0.5*p (3) 0.5*p (3) ns isp18 t w(pclkl) typical pulse duration, cam_pclk low 0.5*p (3) 0.5*p (3) ns t dc(pclk) duty cycle error, cam_pclk 667 1111 ps t j(pclk) cycle jitter (4) , cam_pclk 133 200 ps isp23 t su(dv-pclkh) setup time, cam_d[9:0] valid before cam_pclk 1.82 3.25 ns rising edge isp24 t h(pclkh-dv) hold time, cam_d[9:0] valid after cam_pclk rising 1.82 3.25 ns edge (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the isp module. (3) p = cam_lclk period in ns. (4) maximum cycle jitter supported by cam_lclk input clock. table 6-36. isp switching characteristics ? itu mode no. parameter 1.15 v 1.0 v unit min max min max isp15 t c(xclk) cycle time (1) , cam_xclk period 4.6 4.6 ns isp16 t w(xclkh) typical pulse duration, cam_xclk high 0.5*po (2) 0.5*po (2) ns isp16 t w(xclkl) typical pulse duration, cam_xclk low 0.5*po (2) 0.5*po (2) ns t dc(xclk) duty cycle error, cam_xclk 231 231 ps t j(xclk) jitter standard deviation (3) , cam_xclk 33 33 ps t r(xclk) rise time, cam_xclk 0.93 0.93 ns t f(xclk) fall time, cam_xclk 0.93 0.93 ns (1) related with the cam_xclk maximum and minimum frequencies programmable in the isp module. warning: the camera sensor or the camera module must be disabled to change the frequency configuration. for more information, see the omap35x technical reference manual (trm) [literature number spruf98 (2) po = cam_xclk period in ns (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 194 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-27. isp ? itu mode (1) (2) (1) the unused lines must be grounded and the data bus must be connected to the lower data lines. it is possible to shift the data to 0, 2, or 4 data internal lanes. the different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit mode. (2) the parallel camera in itu mode supports progressive camera modules. submit documentation feedback timing requirements and switching characteristics 195 product preview cam_xclki cam_pclk cam_d[9:0] sof d (0) d(n-1) eof sof d(0) d(n-1) eof isp15 isp16 isp16 isp17 isp23 isp24 isp18 isp18 030-058
6.5.2 display subsystem (dss) 6.5.2.1 lcd display support in bypass mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the display subsystem (dss) provides the logic to display the video frame from external (sdram) or internal (sram) memory on an lcd panel or a tv set. the dss integrates a display controller, a remote frame buffer module (rfbi), and a tv-out module. it can be used in two configurations: lcd display support in: ? bypass mode (rfbi module bypassed) ? rfbi mode (through rfbi module) tv display support (not discussed in this document because of its analog io signals) the two display supports can be active at the same time. two types of lcd panel are supported: thin film transistor (tft) or active matrix technology supertwisted nematic (stn) or passive matrix technology both configurations are discussed in the following paragraphs. 6.5.2.1.1 lcd display in tft mode table 6-37 assumes testing over the recommended operating conditions (see figure 6-28 ). table 6-37. lcd display interface switching characteristics in tft mode (1) (2) no. parameter 1.15 v 1.0 v unit min max min max dl0 t d(pclka-hsynct) delay time, dss_pclk active edge to dss_hsync ?3.9 3.9 ?4.6 4.6 ns transition dl1 t d(pclka-vsynct) delay time, dss_pclk active edge to dss_vsync ?3.9 3.9 ?4.6 4.6 ns transition dl2 t d(pclka-acbiasa) delay time, dss_pclk active edge to dss_acbias ?3.9 3.9 ?4.6 4.6 ns active level dl3 t d(pclka-datav) delay time, dss_pclk active edge to dss_data bus ?3.9 3.9 ?4.6 4.6 ns valid dl4 t c(pclk) cycle time (3) , dss_pclk 13.5 13.5 ns dl5 t w(pclk) pulse duration, dss_pclk low or high 0.45*p (4) 0.55*p (4) 0.45*p (4) 0.55*p (4) ns (1) the capacitive load is equivalent to 25 pf at 1.15 v and 30 pf at 1.0 v. (2) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. (3) the pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the dispc_divisor register. (4) p = dss_pclk period. timing requirements and switching characteristics 196 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-28. lcd display in tft mode (1) (2) (3) (4) (1) the pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) the pixel clock frequency is programmable. (3) all timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. (4) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. 6.5.2.1.2 lcd display in stn mode table 6-38 assumes testing over the recommended operating conditions (see figure 6-29 ). table 6-38. lcd display interface switching characteristics in stn mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max dl3 t d(pclka-datav) delay time, dss_pclk active edge to dss_data bus ?7 7 ?7 7 ns valid dl4 t c(pclk) cycle time (4) , dss_pclk 22.7 22.7 ns dl5 t w(pclk) pulse duration, dss_pclk low or high 0.45*p (5) 0.55*p (5) 0.45*p (5) 0.55*p (5) ns (1) the dss in stn mode is used with 4 or 8 pins only; unused pixel data bits always remain low. (2) the capacitive load is equivalent to 40 pf. (3) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ] . (4) the pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the dispc_divisor register. (5) p = dss_pclk period. submit documentation feedback timing requirements and switching characteristics 197 product preview dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] dl4 dl5 dl3 dl0 dl2 dl1 030-061
6.5.2.2 lcd display support in rfbi mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-29. lcd display in stn mode (1) (2) (3) (4) (5) (1) the pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) all timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. (3) dss_vsync width must be programmed to be as small as possible. (4) the pixel clock frequency is programmable. (5) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ] . table 6-40 and table 6-41 assume testing over the recommended operating conditions (see figure 6-30 through figure 6-32 ). table 6-39. lcd timing conditions ? rfbi mode timing condition parameter value unit input conditions min max t r input signal rise time 15 ns t f input signal fall time 15 ns output conditions c load output load capacitance 30 pf table 6-40. lcd display interface timing requirements in rfbi mode no. parameter 1.15 v 1.0 v 0.95 v unit min max min max min max dr1 t s(dav-rdh) setup time, rfbi_da[15:0] valid to rfbi_rd 2.5 2.5 + i (1) 2.5 2.5 + i (1) tbd tbd ns 6 high dr1 t h(rdh-daiv) hold time, rfbi_rd high to rfbi_da[15:0] 2.5 2.5 + i (1) 2.5 2.5 + i (1) tbd tbd ns 7 invalid (1) i = ((reofftime ? accesstime) * (timeparagranularity + 1) * l4clk 198 timing requirements and switching characteristics submit documentation feedback product preview dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] dl4 dl5 dl3 030-062
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-41. lcd display interface switching characteristics in rfbi mode no. parameter 1.15 v 1.0 v 0.95 v unit min max min max min max dr2 t w(rfbi_wrh) pulse duration, rfbi_wr high a (1) a (1) ns dr3 t w(rfbi_wrl) pulse duration, rfbi_wr low b (2) b (2) ns dr4 t d(rfbi_a0- delay time, rfbi_a0 transition to a (1) ? a (1) + a (1) ? a (1) + ns rfbi_wrl) rfbi_wr low 2.5 2.5 2.5 2.5 dr5 t d(rfbi_a0- delay time, rfbi_a0 transition to c (3) ? c (3) + c (3) ? c (3) + ns rfbi_wrh) rfbi_wr high 2.5 2.5 2.5 2.5 dr6 t d(rfbi_csx- delay time, rfbi_csx (4) low to rfbi_wr c (3) ? c (3) + c (3) ? c (3) + ns rfbi_wrl) low 2.5 2.5 2.5 2.5 dr7 t d(rfbi_wrh- delay time, rfbi_wr high to rfbi_csx (4) d (5) ? d (5) + d (5) ? d (5) + ns rfbi_csh) high 2.5 2.5 2.5 2.5 dr8 t d(rfbi_wrl- delay time, rfbi_wr low to b (2) ? b (2) + b (2) ? b (2) + ns rfbi_dav) rfbi_da[15:0] valid 2.5 2.5 2.5 2.5 dr9 t d(rfbi_a0h- delay time, rfbi_a0 high to rfbi_rd low f (6) ? f (6) + f (6) ? f (6) + ns rfbi_rdl) 2.5 2.5 2.5 2.5 dr10 t d(rfbi_csl- delay time, rfbi_csx (4) low to rfbi_rd g (7) ? g (7) + g (7) ? g (7) + ns rfbi_rdl) low 2.5 2.5 2.5 2.5 dr12 t w(rfbi_rdh) pulse duration, rfbi_rd high j (8) j (8) ns dr13 t w(rfbi_rdl) pulse duration, rfbi_rd low e (9) e (9) ns dr14 t d(rfbi_rdl- delay time, rfbi_rd low to rfbi_csx (4) h (10) ? h (10) + h (10) ? h (10) + ns rfbi_csl) low 2.5 2.5 2.5 2.5 dr15 t d(rfbi_rdh- delay time, rfbi_rd high to rfbi_csx (4) h (10) ? h (10) + h (10) ? h (10) + ns rfbi_csh) high 2.5 2.5 2.5 2.5 t r(rfbi_wr) rise time, rfbi_wr 15 15 ns t f(rfbi_wr) fall time, rfbi_wr 15 15 ns t r(rfbi_a0) rise time, rfbi_a0 15 15 ns t f(rfbi_a0) fall time, rfbi_a0 15 15 ns t r(rfbi_csx) rise time, rfbi_csx 15 15 ns t f(rfbi_csx) fall time, rfbi_csx 15 15 ns t r(rfbi_da[15:0]) rise time, rfbi_da[15:0] 15 15 ns t f(rfbi_da[15:0]) fall time, rfbi_da[15:0] 15 15 ns t r(rfbi_rd) rise time, rfbi_rd 15 15 ns t f(rfbi_rd) fall time, rfbi_rd 15 15 ns (1) a = (weontime) * (timeparagranularity + 1) * l4clk (2) b = (weofftime ? weontime) * (timeparagranularity + 1) * l4clk (3) c = (weontime ? csontime) * (timeparagranularity + 1) * l4clk (4) in rfbi_ncsx, x stands for 0 or 1. (5) d = (csofftime ? weofftime) * (timeparagranularity + 1) * l4clk (6) f = reontime * (timeparagranularity + 1) * l4clk (7) g = (reontime ? csontime) * (timeparagranularity + 1) * l4clk (8) j = (reontime) * l4clk (9) e = (reofftime ? reontime) * (timeparagranularity + 1) * l4clk (10) h = (csofftime ? reofftime) * (timeparagranularity + 1) * l4clk submit documentation feedback timing requirements and switching characteristics 199 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-30. lcd display interface in rfbi mode ? command / data write mode (1) (2) (1) in rfbi_csx, x is equal to 0 or 1. (2) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. figure 6-31. lcd display interface in rfbi mode ? data read mode (1) (2) (1) in rfbi_csx, x is equal to 0 or 1. (2) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. 200 timing requirements and switching characteristics submit documentation feedback product preview rfbi_a0 wecycletime cspulsewidth wecycletime csofftime csontime weontime weofftime data1 data0 csofftime csontime weofftime weontime rfbi_csx rfbi_wr rfbi_da[15:0] rfbi_rd 034-002 data1 data0 rfbi_a0 rfbi_csx rfbi_wr rfbi_da[15:0] rfbi_rd accesstime recycletime accesstime recycletime cspulsewidth csofftime csontime csofftime csontime reontime reofftime reontime reofftime dr0 dr1 034-003
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-32. lcd display interface in rfbi mode ? data read-to-write and write-to-read modes (1) (2) (1) in rfbi_csx, x is equal to 0 or 1. (2) for more information, see the dss chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. submit documentation feedback timing requirements and switching characteristics 201 product preview wecycletime wecycletime accesstime recycletime csofftime csontime csontime csontime csofftime csofftime weofftime weontime weofftime weontime reofftime reontime cspulsewidth cspulsewidth read write write rfbi_a0 rfbi_csx rfbi_wr rfbi_rd rfbi_da[15:0] 034-004
6.6 serial communications interfaces 6.6.1 multichannel buffered serial port (mcbsp) timing 6.6.1.1 mcbsp in normal mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com there are five mcbsp modules called mcbsp1 through mcbsp5. mcbsp provides a full-duplex, direct serial interface between the omap35 15/03 device and other devices in a system such as other application devices or codecs. it can accommodate a wide range of peripherals and clocked frame-oriented protocols (i2s, pcm, and tdm) due to its high level of versatility. the mcbsp1-5 modules may support two types of data transfer at the system level: the full-cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). the half-cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). note that a new data is generated only every clock period, which secures the required hold time. the interface clock (clkx/clkr) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. the omap35 15/03 mcbsp1-5 timing characteristics are described for both rising and falling activation edges. mcbsp1 supports: 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins. 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. the clkx and fsx pins are internally looped back via software configuration, respectively, to the clkr and fsr internal signals for data receive. mcbsp2, 3, 4, and 5 support only the 4-pin mode. the following sections describe the timing characteristics for applications in normal mode (that is, omap35 15/03 mcbspx connected to one peripheral) and tdm applications in multipoint mode. table 6-42. mcbsp timing conditions?normal mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 10 pf table 6-43. mcbsp output clock pulse duration no. parameter 1.15 v 1.0 v unit min max min max t w(clkh) typical pulse duration, mcbsp1_clkr / mcbspx_clkx 0.5*p (2) 0.5*p (2) ns high (1) t w(clkl) typical pulse duration, mcbsp1_clkr / mcbspx_clkx 0.5*p (2) 0.5*p (2) ns low (1) t dc(clk) duty cycle error, mcbsp1_clkr / mcbspx_clkx (1) ?0.75 0.75 ?0.75 0.75 ns (1) in mcbspx, x identifies the mcbsp number: 1, 2, 3, 4, or 5. (2) p = mcbsp1_clkr / mcbspx_clkx clock period. timing requirements and switching characteristics 202 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 6.6.1.1.1 receive timing with rising edge as activation edge table 6-44 through table 6-49 assume testing over the recommended operating conditions (see figure 6-33 through figure 6-34 ). table 6-44. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkae) setup time, mcbspx_dr valid before mcbsp1_clkr / master 3.5 7.7 ns mcbspx_clkx active edge slave 3.7 7.9 ns b4 t h(clkae-drv) hold time, mcbspx_dr valid after mcbsp1_clkr / master 1 1 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsv-clkae) setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr / 3.7 7.9 ns mcbspx_clkx active edge b6 t h(clkae-fsv) hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr / 0.5 0.5 ns mcbspx_clkx active edge (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). table 6-45. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkae-fsv) delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr / 0.7 14.8 0.7 29.6 ns mcbspx_fsx valid (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). table 6-46. mcbsp4 (set #1) timing requirements ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 2.7 7.7 ns mcbspx_clkx active edge slave 3.7 7.9 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after mcbspx_clkx master 1 1 ns active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time mcbspx_fsx valid before mcbspx_clkx active edge 3.7 7.9 ns b6 t h(clkxae-fsxv) hold time mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-48 and table 6-49 table 6-47. mcbsp4 (set #1) switching characteristics ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 16.6 0.7 33.1 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-48 and table 6-49 submit documentation feedback timing requirements and switching characteristics 203 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-48. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 5.6 12 ns mcbspx_clkx active edge slave 5.8 12.2 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after mcbspx_clkx master 1 1 ns active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx active edge 5.8 12.2 ns b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active edge 0.5 0.5 ns (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-46 and table 6-47 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). table 6-49. mcbsp3 (set #1), 4 (set #2), and 5 switching requirements ? rising edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns figure 6-33. mcbsp rising edge receive timing in master mode figure 6-34. mcbsp rising edge receive timing in slave mode (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-46 and table 6-47 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). 6.6.1.1.2 transmit timing with rising edge as activation edge table 6-50 through table 6-55 assume testing over the recommended operating conditions (see figure 6-35 and figure 6-36 ). table 6-50. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.7 7.9 ns active edge (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). timing requirements and switching characteristics 204 submit documentation feedback product preview mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b2 b2 b3 b4 030-068 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b3 b4 b5 b6 030-069
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-50. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements ? rising edge and transmit mode (continued) no. parameter 1.15 v 1.0 v unit min max min max b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge table 6-51. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.8 0.7 29.6 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 14.8 0.6 29.6 ns mcbspx_dx valid slave 0.6 14.8 0.6 29.6 ns (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). table 6-52. mcbsp4 (set #1) timing requirements ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.7 7.9 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-54 . table 6-53. mcbsp4 (set #1) switching characteristics ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to 0.7 16.6 0.7 33.1 ns mcbspx_fsx valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge master 0.6 16.6 0.6 33.1 ns to mcbspx_dx valid slave 0.6 17.3 0.6 33.1 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-54 . table 6-54. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.8 12.2 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-54 . submit documentation feedback timing requirements and switching characteristics 205 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-55. mcbsp 3 (set #1), 4 (set #2), and 5 switching requirements ? rising edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.2 0.7 44.4 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 22.2 0.6 44.4 ns mcbspx_dx valid slave 0.6 22.2 0.6 44.4 ns figure 6-35. mcbsp rising edge transmit timing in master mode figure 6-36. mcbsp rising edge transmit timing in slave mode (1) in mcbspx, x identifies the mcbsp number: 3, 4 or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in the table above. for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). 6.6.1.1.3 receive timing with falling edge as activation edge table 6-56 through table 6-61 assume testing over the recommended operating conditions (see figure 6-37 and figure 6-38 ). table 6-56. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkae) setup time, mcbspx_dr valid before master 3.5 7.7 ns mcbsp1_clkr / mcbspx_clkx active edge slave 3.7 7.9 ns b4 t h(clkae-drv) hold time, mcbspx_dr valid after master 1 1 ns mcbsp1_clkr / mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsv-clkae) setup time, mcbsp1_fsr / mcbspx_fsx valid before 3.7 7.9 ns mcbsp1_clkr /mcbspx_clkx active edge b6 t h(clkae-fsv) hold time, mcbsp1_fsr / mcbspx_fsx valid after 0.5 0.5 ns mcbsp1_clkr /mcbspx_clkx active edge (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). 206 timing requirements and switching characteristics submit documentation feedback product preview mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b2 b2 b8 030-070 mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b8 b5 b6 030-071
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-57. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkae-fsv) delay time, mcbsp1_clkr / mcbspx_clkx active edge to 0.7 14.8 0.7 29.6 ns mcbsp1_fsr / mcbspx_fsx valid (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). table 6-58. mcbsp4 (set #1) timing requirements ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 2.7 7.7 ns mcbspx_clkx active edge slave 3.7 7.9 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after master 1 1 ns mcbspx_clkx active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time mcbspx_fsx valid before mcbspx_clkx active 3.7 7.9 ns edge b6 t h(clkxae-fsxv) hold time mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-60 table 6-59. mcbsp4 (set #1) switching characteristics ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 16.6 0.7 33.1 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-60 table 6-60. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b3 t su(drv-clkxae) setup time, mcbspx_dr valid before master 5.6 12 ns mcbspx_clkx active edge slave 5.8 12.2 ns b4 t h(clkxae-drv) hold time, mcbspx_dr valid after mcbspx_clkx master 1 1 ns active edge slave 0.4 0.4 ns b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx active 5.8 12.2 ns edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx active 0.5 0.5 ns edge (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in the table above. for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). submit documentation feedback timing requirements and switching characteristics 207 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-61. mcbsp3 (set #1), 4 (set #2), and 5 switching requirements ? falling edge and receive mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 22.2 0.7 44.4 ns valid (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in the table above. for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). figure 6-37. mcbsp falling edge receive timing in master mode figure 6-38. mcbsp falling edge receive timing in slave mode 6.6.1.1.4 transmit timing with falling edge as activation edge table 6-62 through table 6-67 assume testing over the recommended operating conditions (see figure 6-39 and figure 6-40 ). table 6-62. mcbsp1, 2, and 3 (sets #2 and #3) timing requirements ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 3.7 7.9 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). table 6-63. mcbsp1, 2, and 3 (sets #2 and #3) switching characteristics ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 14.8 0.7 29.6 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 14.8 0.6 29.6 ns mcbspx_dx valid slave 0.6 14.8 0.6 29.6 ns (1) in mcbspx, x identifies the mcbsp number: 1, 2, or 3. note that for the mcbsp3, these timings concern only set #2 (multiplexing mode on uart pins) and set #3 (multiplexing mode on mcbsp1 pins). timing requirements and switching characteristics 208 submit documentation feedback product preview mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b2 b2 b3 b4 030-072 mcbspx_clkr mcbspx_fsr mcbspx_dr d7 d6 d5 b3 b4 b5 b6 030-073
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-64. mcbsp4 (set #1) timing requirements ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before 3.7 7.9 ns mcbspx_clkx active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-66 . table 6-65. mcbsp4 (set #1) switching characteristics ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx 0.7 16.6 0.7 33.1 ns valid b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 16.6 0.6 33.1 ns mcbspx_dx valid slave 0.6 17.3 0.6 33.1 ns (1) in mcbspx, x identifies the mcbsp number: 4. note that for the mcbsp4, these timings concern only set #1: multiplexing mode by default. the mcbsp4 is also multiplexed on gpmc pins (set #2): the corresponding timings are specified in table 6-66 . table 6-66. mcbsp3 (set #1), 4 (set #2), and 5 timing requirements ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b5 t su(fsxv-clkxae) setup time, mcbspx_fsx valid before mcbspx_clkx 5.8 12.2 ns active edge b6 t h(clkxae-fsxv) hold time, mcbspx_fsx valid after mcbspx_clkx 0.5 0.5 ns active edge (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-66 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). table 6-67. mcbsp3 (set #1), 4 (set #2), and 5 switching requirements ? falling edge and transmit mode (1) no. parameter 1.15 v 1.0 v unit min max min max b2 t d(clkxae-fsxv) delay time, mcbspx_clkx active edge to mcbspx_fsx valid 0.7 22.2 0.7 44.4 ns b8 t d(clkxae-dxv) delay time, mcbspx_clkx active edge to master 0.6 22.2 0.6 44.4 ns mcbspx_dx valid slave 0.6 22.2 0.6 44.4 ns (1) in mcbspx, x identifies the mcbsp number: 3, 4, or 5. note that for the mcbsp3, these timings concern only set #1: multiplexing mode by default. the mcbsp3 is also multiplexed on uart pins (set #2) and on mcbsp1 pins (set #3): the corresponding timings are specified in table 6-66 . for the mcbsp4, these timings concern only set #2 (multiplexing mode on gpmc pins). figure 6-39. mcbsp falling edge transmit timing in master mode submit documentation feedback timing requirements and switching characteristics 209 product preview mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b2 b2 b8 030-074
6.6.1.2 mcbsp in tdm?multipoint mode (mcbsp3) omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-40. mcbsp falling edge transmit timing in slave mode for tdm application in multipoint mode, omap35 15/03 is considered as a slave. table 6-69 and table 6-70 assume testing over the operating conditions and electrical characteristic conditions described below. table 6-68. mcbsp3 timing conditions?tdm in multipoint mode timing condition parameter value unit min max input conditions t r input signal rising time 1.0 8.5 ns t f input signal falling time 1.0 8.5 ns output conditions c load output load capacitance 40 pf table 6-69. mcbsp3 timing requirements?tdm in multipoint mode (1) no. parameter 1.15 v 1.0 v unit min max min max t w(clkh) cycle time, mcbsp3_clkx 162.8 162.8 ns t w(clkh) typical pulse duration, mcbsp3_clkx high 0.5*p (2) 0.5*p (2) ns t w(clkl) typical pulse duration, mcbsp3_clkx low 0.5*p (2) 0.5*p (2) ns t dc(clk) duty cycle error, mcbsp3_clkx ?8.14 8.14 ?8.14 8.14 ns b3 (3) t su(drv-clkae) setup time, mcbsp3_dr valid before 9 9 ns mcbsp3_clkx active edge b4 (3) t h(clkae-drv) hold time, mcbsp3_dr valid after mcbsp3_clkx 2.4 2.4 ns active edge b5 (3) t su(fsv-clkae) setup time, mcbsp3_fsx valid before 9 9 ns mcbsp3_clkx active edge b6 (3) t h(clkae-fsv) hold time, mcbsp3_fsx valid after 2.4 2.4 ns mcbsp3_clkx active edge (1) for mcbsp3, these timings concern only set #3 (multiplexing mode in mcbsp1 pins). (2) p = mcbsp3_clkx period in ns (3) see section 6.6.1.1 , mcbsp in normal mode for corresponding figures. table 6-70. mcbsp3 switching characteristics?tdm in multipoint mode (1) no. parameter 1.15 v 1.0 v unit min max min max b8 (2) t d(clkxae-dxv) delay time, mcbsp3_clkx active edge to 0.6 16.8 0.6 29.6 ns mcbsp3_dx valid (1) for mcbsp3, these timings concern only set #3 (multiplexing mode in mcbsp1 pins). (2) see section 6.6.1.1 , mcbsp in normal mode for corresponding figures. timing requirements and switching characteristics 210 submit documentation feedback product preview mcbspx_clkx mcbspx_fsx mcbspx_dx d7 d6 d5 b8 b5 b6 030-075
6.6.2 multichannel serial port interface (mcspi) timing 6.6.2.1 mcspi in slave mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the multichannel spi is a master/slave synchronous serial bus. the mcspi1 module supports up to four peripherals and the others (mcspi2, mcspi3, and mcspi4) support up to two peripherals. the following timings are applicable to the different configurations of mcspi in master/slave mode for any mcspi and any channel (n). table 6-71 and table 6-72 assume testing over the recommended operating conditions (see figure 6-41 ). table 6-71. mcspi interface timing requirements ? slave mode (1) (2) no. parameter 1.15 v 1.0 v unit min max min max ss0 t c(clk) cycle time, mcspix_clk 41.7 83.3 ns ss1 t w(clk) pulse duration, mcspix_clk high or low 0.45*p (3) 0.55*p (3) 0.45*p (3) 0.55*p (3) ns ss2 t su(simov-clkae) setup time, mcspix_simo valid before mcspix_clk 4.2 9.5 ns active edge ss3 t h(simov-clkae) hold time, mcspix_simo valid after mcspix_clk active 4.6 9.9 ns edge ss4 t su(cs0v-clkfe) setup time, mcspix_cs0 valid before mcspix_clk first 13.8 28.6 ns edge ss5 t h(cs0i-clkle) hold time, mcspix_cs0 invalid after mcspix_clk last 13.8 28.6 ns edge (1) the input timing requirements are given by considering a rise time and a fall time of 4 ns. (2) in mcspix, x is equal to 1, 2, 3, or 4. (3) p = mcspix_clk clock period table 6-72. mcspi interface switching requirements (1) (2) (3) (4) no. parameter 1.15 v 1.0 v unit min max min max ss6 t d(clkae-somiv) delay time, mcspix_clk active edge to mcspix_somi 1.8 15.9 3.2 31.7 ns shifted ss7 t d(cs0ae-somiv) delay time, mcspix_cs0 active edge to modes 0 and 2 15.9 31.7 ns mcspix_somi shifted (1) the capacitive load is equivalent to 20 pf. (2) in mcspix, x is equal to 1, 2, 3, or 4. (3) the polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. (4) this timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and capture input data. submit documentation feedback timing requirements and switching characteristics 211 product preview
6.6.2.2 mcspi in master mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-41. mcspi interface ? transmit and receive in slave mode (1) (2) (1) the active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the bit mspi_chconfx[0] = pha and the bit mspi_chconfx[1] = pol. (2) the polarity of mcspix_csi is software configurable with the bit mspi_chconfx[6] = epol in mcspix, x is equal to 1, 2, 3, or 4. table 6-73 and table 6-74 assume testing over the recommended operating conditions (see figure 6-42 ). table 6-73. mcspi1, 2, and 4 interface timing requirements ? master mode (1) (2) no. parameter 1.15 v 1.0 v unit min max min max sm2 t su(somiv-clkae) setup time, mcspix_somi valid before mcspix_clk 1.1 1.5 ns active edge sm3 t h(somiv-clkae) hold time, mcspix_somi valid after mcspix_clk active 1.9 2.8 ns edge (1) the input timing requirements are given by considering a rise time and a fall time of 4 ns. (2) in mcspix, x is equal to 1, 2, or 4. in mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. timing requirements and switching characteristics 212 submit documentation feedback product preview mcspix_cs0(epol=1) mcspix_clk(pol=0)mcspix_clk(pol=1) mcspix_simomcspix_somi mcspix_cs0(epol=1) mcspix_clk(pol=0)mcspix_clk(pol=1) mcspix_simomcspix_somi bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 ss4 ss5 ss6 ss3 ss1 ss0 ss2 ss1 ss0 ss4 ss5 ss3 ss1 ss0 ss1 ss0 ss2 ss6 ss7 mode 0 & 2mode 1 & 3 030-076
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-74. mcspi1, 2, and 4 interface switching characteristics ? master mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max sm0 t c(clk) cycle time, mcspix_clk 20.8 41.7 ns sm1 t w(clk) pulse duration, mcspix_clk high or low 0.45*p (4) 0.55*p (4) 0.45*p ( 0.55*p (4) ns 4) sm4 t d(clkae-simov) delay time, mcspix_clk active edge to mcspix_simo ?2.1 5 ?2.1 11.3 ns shifted sm5 t d(csna-clkfe) delay time, mcspix_csi active to modes 1 a (5) ? 3.1 a (5) ? ns mcspix_clk first edge and 3 4.4 modes 0 b (6) ? 3.1 b (6) ? ns and 2 4.4 sm6 t d(clkle-csni) delay time, mcspix_clk last edge to modes 1 b (6) ? 3.1 b (6) ? ns mcspix_csi inactive and 3 4.4 modes 0 a (5) ? 3.1 a (5) ? ns and 2 4.4 sm7 t d(csnae-simov) delay time, mcspix_csi active edge to modes 0 5.0 11.3 ns mcspix_simo shifted and 2 (1) timings are given for a maximum load capacitance of 20 pf for spix_csn signals, 30 pf for spix_clk and spix_simo signals with x = 1 or 2, and 20 pf for spi4_clk and spi4_simo signals. (2) in mcspix, x is equal to 1, 2, or 4. in mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. (3) the polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. (4) p = mcspix_clk clock period (5) case p = 20.8 ns, a = (tcs+0.5)*p (tcs is a bit field of mspi_chconfx[26:25] register). case p > 20.8 ns, a = tcs*p (tcs is a bitfield of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. (6) b = tcs*p (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. table 6-75 and table 6-76 assume testing over the recommended operating conditions (see figure 6-42 ). table 6-75. mcspi 3 interface timing requirements ? master mode (1) (2) no. parameter 1.15 v 1.0 v unit min max min max sm2 t su(somiv-clkae) setup time, mcspi3_somi valid before 1.5 4.3 ns mcspi3_clk active edge sm3 t h(somiv-clkae) hold time, mcspi3_somi valid after mcspi3_clk 2.8 5.9 ns active edge (1) the input timing requirements are given by considering a rise time and a fall time of 4 ns. (2) in mcspi3_csn, n is equal to 0 or 1. the polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. table 6-76. mcspi3 interface switching requirements ? master mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max sm0 t c(clk) cycle time, mcspix_clk 41.7 83.3 ns sm1 t w(clk) pulse duration, mcspix_clk high or low 0.45*p (4) 0.55*p (4) 0.45*p (4) 0.55*p (4) ns sm4 t d(clkae-simov) delay time, mcspix_clk active edge to ?2.1 11.3 ?5.3 23.6 ns mcspix_simo shifted (1) the capacitive load is equivalent to 20 pf. (2) in mcspi3_csn, n is equal to 0 or 1. the polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable. (3) this timing applies to all configurations regardless of mcspi3_clk polarity and which clock edges are used to drive output data and capture input data. (4) p = mcspi3_clk clock period submit documentation feedback timing requirements and switching characteristics 213 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-76. mcspi3 interface switching requirements ? master mode (continued) no. parameter 1.15 v 1.0 v unit min max min max sm5 t d(csna-clkfe) delay time, mcspix_csi active modes 1 ?4.4 + a (5) ?10.1 + a (5) ns to mcspix_clk first edge and 3 modes 0 ?4.4 + b (6) ?10.1 + b (6) ns and 2 sm6 t d(clkle-csni) delay time, mcspix_clk last modes 1 ?4.4 + a (5) ?10.1 + a (5) ns edge to mcspix_csi inactive and 3 modes 0 ?4.4 + b (6) ?10.1 + b (6) ns and 2 sm7 t d(csnae-simov) delay time, mcspix_csi active modes 0 11.3 23.6 ns edge to mcspix_simo shifted and 2 (5) case p = 20.8 ns, a = (tcs + 0.5)*p (tcs is a bit field of mspi_chconfx[26:25] register). case p > 20.8 ns, a = tcs*p (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. (6) b = tcs*p (tcs is a bit field of mspi_chconfx[26:25] register). for more information, see the mcspi chapter of the omap35x technical reference manual (trm) [literature number spruf98 ]. figure 6-42. mcspi interface ? transmit and receive in master mode (1) (2) (3) (1) the active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the bit mspi_chconfx[0] = pha and the bit mspi_chconfx[1] = pol. timing requirements and switching characteristics 214 submit documentation feedback product preview mcspix_csn(epol=1) mcspix_clk(pol=0)mcspix_clk(pol=1) mcspix_simomcspix_somi mcspix_csn(epol=1) mcspix_clk(pol=0)mcspix_clk(pol=1) mcspix_simomcspix_somi bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit n-4 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 bit n-1 bit n-2 bit n-3 bit 1 bit 0 sm5 sm6 sm4 sm3 sm1 sm0 sm2 sm1 sm0 sm5 sm6 sm3 sm1 sm0 sm1 sm0 sm2 sm4 sm7 mode 0 & 2mode 1 & 3 030-077
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 (2) the polarity of mcspix_csi is software configurable with the bit mspi_chconfx[6] = epol. (3) in mcspix, x is equal to 1. in mcspix_csn, n is equal to 0, 1, 2, or 3. submit documentation feedback timing requirements and switching characteristics 215 product preview
6.6.3 multiport full-speed universal serial bus (usb) interface 6.6.3.1 multiport full-speed universal serial bus (usb) ? unidirectional standard 6-pin mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the omap35 15/03 processor provides three usb ports working in full- and low-speed data transactions (up to 12mbit/s). connected to either a serial link controller (tll modes) or a serial phy (phy interface modes) it supports: 6-pin (tx: dat/se0 or tx: dp/dm) unidirectional mode 4-pin bidirectional mode 3-pin bidirectional mode table 6-78 and table 6-79 assume testing over the recommended operating conditions (see figure 6-43 ). table 6-77. low-/full-speed usb timing conditions ? unidirectional standard 6-pin mode timing condition parameter value unit input conditions t r input signal rise time 2.0 ns t f input signal fall time 2.0 ns output conditions c load output load capacitance 15.0 pf table 6-78. low-/full-speed usb timing requirements ? unidirectional standard 6-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu1 t d(vp,vm) time duration, mmx_rxdp and mmx_rxdm low together during 14.0 14.0 ns transition fsu2 t d(vp,vm) time duration, mmx_rxdp and mmx_rxdm high together during 8.0 8.0 ns transition fsu3 t d(rcvu0) time duration, mmx_rrxcv undefine during a single end 0 14.0 14.0 ns (mmx_rxdp and mmx_rxdm low together) fsu4 t d(rcvu1) time duration, mmx_rxrcv undefine during a single end 1 8.0 8.0 ns (mmx_rxdp and mmx_rxdm high together) table 6-79. low-/full-speed usb switching characteristics ? unidirectional standard 6-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu5 t d(txenl-datv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu6 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu7 t s(dat-se0) skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns fsu8 t d(dati-txenh) delay time, mmx_txdat invalid to mmx_txen_n high 81.8 81.8 ns fsu9 t d(se0i-txenh) delay time, mmx_txse0 invalid to mmx_txen_n high 81.8 81.8 ns t r(do) rise time, mmx_txen_n 4.0 4.0 ns t f(do) fall time, mmx_txen_n 4.0 4.0 ns t r(do) rise time, mmx_txdat 4.0 4.0 ns t f(do) fall time, mmx_txdat 4.0 4.0 ns t r(do) rise time, mmx_txse0 4.0 4.0 ns t f(do) fall time, mmx_txse0 4.0 4.0 ns timing requirements and switching characteristics 216 submit documentation feedback product preview
6.6.3.2 multiport full-speed universal serial bus (usb) ? bidirectional standard 4-pin mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 in mmx, x is equal to 0, 1, or 2. figure 6-43. low-/full-speed usb ? unidirectional standard 6-pin mode table 6-81 and table 6-82 assume testing over the recommended operating conditions (see figure 6-44 ). table 6-80. low-/full-speed usb timing conditions ? bidirectional standard 4-pin mode timing condition parameter value unit input conditions t r input signal rise time 2.0 ns t f input signal fall time 2.0 ns output conditions c load output load capacitance 15.0 pf table 6-81. low-/full-speed usb timing requirements ? bidirectional standard 4-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu10 t d(dat,se0) time duration, mmx_txdat and mmx_txse0 low together 14.0 14.0 ns during transition fsu11 t d(dat,se0) time duration, mmx_txdat and mmx_txse0 high together 8.0 8.0 ns during transition fsu12 t d(rcvu0) time duration, mmx_rrxcv undefine during a single end 0 14.0 14.0 ns (mmx_txdat and mmx_txse0 low together) fsu13 t d(rcvu1) time duration, mmx_rxrcv undefine during a single end 1 8.0 8.0 ns (mmx_txdat and mmx_txse0 high together) table 6-82. low-/full-speed usb switching characteristics ? bidirectional standard 4-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu14 t d(txenl-datv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu15 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu16 t s(dat-se0) skew between mmx_txdat and mmx_txse0 1.5 1.5 ns transition fsu17 t d(datv-txenh) delay time, mmx_txdat invalid before mmx_txen_n 81.8 81.8 ns high submit documentation feedback timing requirements and switching characteristics 217 product preview mmx_txen_n mmx_txdat mmx_txse0 mmx_rxdp mmx_rxdm mmx_rxrcv fsu5 fsu6 fsu7 fsu1 fsu1 fsu2 fsu2 fsu3 fsu4 fsu8 fsu9 transmit receive 030-080
6.6.3.3 multiport full-speed universal serial bus (usb) ? bidirectional standard 3-pin mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-82. low-/full-speed usb switching characteristics ? bidirectional standard 4-pin mode (continued) no. parameter 1.15 v 1.0 v unit min max min max fsu18 t d(se0v-txenh) delay time, mmx_txse0 invalid before mmx_txen_n 81.8 81.8 ns high t r(txen) rise time, mmx_txen_n 4.0 4.0 ns t f(txen) fall time, mmx_txen_n 4.0 4.0 ns t r(dat) rise time, mmx_txdat 4.0 4.0 ns t f(dat) fall time, mmx_txdat 4.0 4.0 ns t r(se0) rise time, mmx_txse0 4.0 4.0 ns t f(se0) fall time, mmx_txse0 4.0 4.0 ns in mmx, x is equal to 0, 1, or 2. figure 6-44. low-/full-speed usb ? bidirectional standard 4-pin mode table 6-84 and table 6-85 assume testing over the recommended operating conditions below (see figure 6-45 ). table 6-83. low-/full-speed usb timing conditions ? bidirectional standard 3-pin mode timing condition parameter value unit input conditions t r input signal rise time 2.0 ns t f input signal fall time 2.0 ns output conditions c load output load capacitance 15.0 pf table 6-84. low-/full-speed usb timing requirements ? bidirectional standard 3-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu19 t d(dat,se0) time duration, mmx_txdat and mmx_txse0 low together 14.0 14.0 ns during transition fsu20 t d(dat,se0) time duration, mmx_tsdat and mmx_txse0 high 8.0 8.0 ns together during transition timing requirements and switching characteristics 218 submit documentation feedback product preview mmx_txen_n mmx_txdat mmx_txse0 mmx_rxrcv fsu16 fsu14 fsu15 fsu10 fsu10 fsu11 fsu11 fsu12 fsu13 fsu17 fsu18 transmit receive 030-081
6.6.3.4 multiport full-speed universal serial bus (usb) ? unidirectional tll 6-pin mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-85. low-/full-speed usb switching characteristics ? bidirectional standard 3-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsu21 t d(txenl-datv) delay time, mmx_txen_n low to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsu22 t d(txenl-se0v) delay time, mmx_txen_n low to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsu23 t s(dat-se0) skew between mmx_txdat and mmx_txse0 1.5 1.5 ns transition fsu24 t d(dati-txenh) delay time, mmx_txdat invalid to mmx_txen_n 81.8 81.8 ns high fsu25 t d(se0i-txenh) delay time, mmx_txse0 invalid to mmx_txen_n 81.8 81.8 ns high t r(do) rise time, mmx_txen_n 4.0 4.0 ns t f(do) fall time, mmx_txen_n 4.0 4.0 ns t r(do) rise time, mmx_txdat 4.0 4.0 ns t f(do) fall time, mmx_txdat 4.0 4.0 ns t r(do) rise time, mmx_txse0 4.0 4.0 ns t f(do) fall time, mmx_txse0 4.0 4.0 ns in mmx, x is equal to 0, 1, or 2. figure 6-45. low-/full-speed usb ? bidirectional standard 3-pin mode table 6-87 and table 6-88 assume testing over the recommended operating conditions (see figure 6-46 ). table 6-86. low-/full-speed usb timing conditions ? unidirectional tll 6-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 15 pf table 6-87. low-/full-speed usb timing requirements ? unidirectional tll 6-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut1 t d(se0,dat) time duration, mmx_txse0 and mmx_txdat low 14 14 ns together during transition fsut2 t d(se0,dat) time duration, mmx_txse0 and mmx_txdat high 8 8 ns together during transition submit documentation feedback timing requirements and switching characteristics 219 product preview mmx_txen_n mmx_txdat mmx_txse0 fsu23 fsu21 fsu22 fsu19 fsu19 fsu20 fsu20 fsu24 fsu25 transmit receive 030-082
6.6.3.5 multiport full-speed universal serial bus (usb) ? bidirectional tll 4-pin mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-88. low-/full-speed usb switching characteristics ? unidirectional tll 6-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut3 t d(txenh-dpv) delay time, mmx_txen_n high to mmx_rxdp valid 81.8 84.8 81.8 84.8 ns fsut4 t d(txenh-dmv) delay time, mmx_txen_n high to mmx_rxdm valid 81.8 84.8 81.8 84.8 ns fsut5 t d(dpi-txenl) delay time, mmx_rxdp invalid mmx_txen_n low 81.8 81.8 ns fsut6 t d(dmi-txenl) delay time, mmx_rxdm invalid mmx_txen_n low 81.8 81.8 ns fsut7 t s(dp-dm) skew between mmx_rxdp and mmx_rxdm 1.5 1.5 ns transition fsut8 t s(dp,dm-rcv) skew between mmx_rxdp, mmx_rxdm, and 1.5 1.5 ns mmx_rxrcv transition t r(rxrcv) rise time, mmx_rxrcv 4 4 ns t f(rxrcv) fall time, mmx_rxrcv 4 4 ns t r(dp) rise time, mmx_rxdp 4 4 ns t f(dp) fall time, mmx_rxdp 4 4 ns t r(dm) rise time, mmx_rxdm 4 4 ns t f(dm) fall time, mmx_rxdm 4 4 ns in mmx, x is equal to 0, 1, or 2. figure 6-46. low-/full-speed usb ? unidirectional tll 6-pin mode table 6-90 and table 6-91 assume testing over the recommended operating conditions (see figure 6-47 ). table 6-89. low-/full-speed usb timing conditions ? bidirectional tll 4-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 15 pf timing requirements and switching characteristics 220 submit documentation feedback product preview mmx_txen_n mmx_txdat mmx_txse0 mmx_rxdp mmx_rxdm mmx_rxrcv fsut3 fsut5 fsut4 fsut6 fsut7 fsut8 fsut1 fsut1 fsut2 fsut2 transmit receive 030-083
6.6.3.6 multiport full-speed universal serial bus (usb) ? bidirectional tll 3-pin mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-90. low-/full-speed usb timing requirements ? bidirectional tll 4-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut9 t d(dat,se0) time duration, mmx_txdat and mmx_txse0 low 14 14 ns together during transition fsut10 t d(dat,se0) time duration, mmx_tsdat and mmx_txse0 high 8 8 ns together during transition table 6-91. low-/full-speed usb switching characteristics ? bidirectional tll 4-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut11 t d(txenl-datv) delay time, mmx_txen_n active to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsut12 t d(txenl-se0v) delay time, mmx_txen_n active to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsut13 t s(dat-se0) skew between mmx_txdat and mmx_txse0 1.5 1.5 ns transition fsut14 t s(dp,dm-rcv) skew between mmx_rxdp, mmx_rxdm, and 1.5 1.5 ns mmx_rxrcv transition fsut15 t d(dati-txenl) delay time, mmx_txse0 invalid to mmx_txen_n low 81.8 81.8 ns fsut16 t d(se0i-txenl) delay time, mmx_txdat invalid to mmx_txen_n low 81.8 81.8 ns t r(rcv) rise time, mmx_rxrcv 4 4 ns t f(rcv) fall time, mmx_rxrcv 4 4 ns t r(dat) rise time, mmx_txdat 4 4 ns t f(dat) fall time, mmx_txdat 4 4 ns t r(se0) rise time, mmx_txse0 4 4 ns t f(se0) fall time, mmx_txse0 4 4 ns in mmx, x is equal to 0, 1, or 2. figure 6-47. low-/full-speed usb ? bidirectional tll 4-pin mode table 6-93 and table 6-94 assume testing over the recommended operating conditions (see figure 6-48 ). table 6-92. low-/full-speed usb timing conditions ? bidirectional tll 3-pin mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns submit documentation feedback timing requirements and switching characteristics 221 product preview mmx_txen_n mmx_txdat mmx_txse0 mmx_rxrcv fsut13 fsut11 fsut12 fsut9 fsut9 fsut10 fsut10 fsut14 fsut15 fsut16 receive transmit 030-084
6.6.4 multiport high-speed universal serial bus (usb) timing omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-92. low-/full-speed usb timing conditions ? bidirectional tll 3-pin mode (continued) timing condition parameter value unit output conditions c load output load capacitance 15 pf table 6-93. low-/full-speed usb timing requirements ? bidirectional tll 3-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut17 t d(dat,se0) time duration, mmx_txdat and mmx_txse0 low 14 14 ns together during transition fsut18 t d(dat,se0) time duration, mmx_tsdat and mmx_txse0 high 8 8 ns together during transition table 6-94. low-/full-speed usb switching characteristics ? bidirectional tll 3-pin mode no. parameter 1.15 v 1.0 v unit min max min max fsut19 t d(txenh-datv) delay time, mmx_txen_n high to mmx_txdat valid 81.8 84.8 81.8 84.8 ns fsut20 t d(txenh-se0v) delay time, mmx_txen_n high to mmx_txse0 valid 81.8 84.8 81.8 84.8 ns fsut21 t s(dat-se0) skew between mmx_txdat and mmx_txse0 1.5 1.5 ns transition fsut22 t d(dati-txenl) delay time, mmx_txdat invalid mmx_txen_n low 81.8 81.8 ns fsut23 t d(se0i-txenl) delay time, mmx_txse0 invalid mmx_txen_n low 81.8 81.8 ns t r(dat) rise time, mmx_txdat 4 4 ns t f(dat) fall time, mmx_txdat 4 4 ns t r(se0) rise time, mmx_txse0 4 4 ns t f(se0) fall time, mmx_txse0 4 4 ns t r(do) rise time, mmx_txse0 4 4 ns t f(do) fall time, mmx_txse0 4 4 ns in mmx, x is equal to 0, 1, or 2. figure 6-48. low-/full-speed usb ? bidirectional tll 3-pin mode in addition to the full-speed usb controller, a high-speed (hs) usb otg controller is instantiated inside omap35 15/03. it allows high-speed transactions (up to 480 mbit/s) on the usb ports 0, 1, 2, and 3. port 0: ? 12-bit slave mode (sdr) port 1 and port 2: ? 12-bit master mode (sdr) ? 12-bit tll master mode (sdr) timing requirements and switching characteristics 222 submit documentation feedback product preview mmx_txen_n mmx_txdat mmx_txse0 fsut21 fsut19 fsut20 fsut17 fsut17 fsut18 fsut18 fsut22 fsut23 transmit receive 030-085
6.6.4.1 high-speed universal serial bus (usb) on port 0 ? 12-bit slave mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 ? 8-bit tll master mode (ddr) port 3: ? 12-bit tll master mode (sdr) ? 8-bit tll master mode (ddr) table 6-96 and table 6-97 assume testing over the recommended operating conditions (see figure 6-49 ). table 6-95. high-speed usb timing conditions ? 12-bit slave mode timing condition parameter value unit input conditions t r input signal rising time 2.00 ns t f input signal falling time 2.00 ns output conditions c load output load capacitance 3.50 pf table 6-96. high-speed usb timing requirements ? 12-bit slave mode (1) no. parameter 1.15 v unit min max hsu0 f p(clk) hsusb0_clk clock frequency (2) (3) 60.03 mhz t j(clk) cycle jitter (3) , hsusb0_clk 500.00 ps hsu3 t s(dirv-clkh) setup time, hsusb0_dir valid before hsusb0_clk rising edge 6.7 ns t s(nxtv-clkh) setup time, hsusb0_nxt valid before hsusb0_clk rising edge 6.7 ns hsu4 t h(clkh-diriv) hold time, hsusb0_dir valid after hsusb0_clk rising edge 0.0 ns t h(clkh-nxt/iv) hold time, hsusb0_nxt valid after hsusb0_clk rising edge 0.0 ns hsu5 t s(datav-clkh) setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge 6.7 ns hsu6 t h(clkh-dativ) hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge 0.0 ns (1) the timing requirements are assured for the cycle jitter error condition specified. (2) related with the input maximum frequency supported by the i/f module. (3) maximum cycle jitter supported by clk input clock. table 6-97. high-speed usb switching characteristics ? 12-bit slave mode no. parameter 1.15 v unit min max hsu1 t d(clkl-stpv) delay time, hsusb0_clk high to output usb0_stp valid 9.0 ns t d(clkl-stpiv) delay time, hsusb0_clk high to output usb0_stp invalid 0.5 ns hsu2 t d(clkl-dv) delay time, hsusb0_clk high to output hsusb0_data[0:7] valid 9.0 ns t d(clkl-div) delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid 0.5 ns t r(do) rising time, output signals 2.0 ns t f(do) falling time, output signals 2.0 ns submit documentation feedback timing requirements and switching characteristics 223 product preview
6.6.4.2 high-speed universal serial bus (usb) on ports 1 and 2 ? 12-bit master mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-49. high-speed usb ? 12-bit slave mode table 6-99 and table 6-100 assume testing over the recommended operating conditions (see figure 6-50 ). table 6-98. high-speed usb timing conditions ? 12-bit master mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 3 pf table 6-99. high-speed usb timing requirements ? 12-bit master mode (1) no. parameter 1.15 v unit min max hsu3 t s(dirv-clkh) setup time, hsusbx_dir valid before hsusbx_clk rising edge 9.3 ns t s(nxtv-clkh) setup time, hsusbx_nxt valid before hsusbx_clk rising edge 9.3 ns hsu4 t h(clkh-diriv) hold time, hsusbx_dir valid after hsusbx_clk rising edge 0.2 ns t h(clkh-nxt/iv) hold time, hsusbx_nxt valid after hsusbx_clk rising edge 0.2 ns hsu5 t s(datav-clkh) setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge 9.3 ns hsu6 t h(clkh-dativ) hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 0.2 ns (1) in hsusbx, x is equal to 1 or 2. table 6-100. high-speed usb switching characteristics ? 12-bit master mode (1) n o. parameter 1.15 v unit min max hsu0 f p(clk) hsusbx_clk clock frequency 60 mhz t j(clk) jitter standard deviation (2) , hsusbx_clk 200 ps hsu1 t d(clkl-stpv) delay time, hsusbx_clk high to output hsusbx_stp valid 13 ns t d(clkl-stpiv) delay time, hsusbx_clk high to output hsusbx_stp invalid 2 ns hsu2 t d(clkl-dv) delay time, hsusbx_clk high to output hsusbx_data[0:7] valid 13 ns t d(clkl-div) delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid 2 ns (1) in hsusbx, x is equal to 1 or 2. (2) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 224 submit documentation feedback product preview hsusb0_clk hsusb0_stp hsusb0_dir_&_nxt hsusb0_data[7:0] data_out data_in hsu1 hsu0 hsu1 hsu4 hsu2 hsu2 hsu6 hsu3 hsu5 030-086
6.6.4.3 high-speed universal serial bus (usb) on ports 1, 2, and 3 ? 12-bit tll master mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-100. high-speed usb switching characteristics ? 12-bit master mode (continued) n o. parameter 1.15 v unit min max t r(do) rise time, output signals 2 ns t f(do) fall time, output signals 2 ns in hsusbx, x is equal to 1 or 2. figure 6-50. high-speed usb ? 12-bit master mode table 6-102 and table 6-103 assume testing over the recommended operating conditions (see figure 6-51 ). table 6-101. high-speed usb timing conditions ? 12-bit tll master mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 3 pf table 6-102. high-speed usb timing requirements ? 12-bit tll master mode (1) no. parameter 1.15 v unit min max hsu2 t s(stpv-clkh) setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns hsu3 t s(clkh-stpiv) hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns hsu4 t s(datav-clkh) setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge 6 ns hsu5 t h(clkh-dativ) hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge 0 ns (1) in hsusbx, x is equal to 1, 2, or 3. table 6-103. high-speed usb switching characteristics ? 12-bit tll master mode (1) no. parameter 1.15 v unit min max hsu0 f p(clk) hsusbx_tll_clk clock frequency 60 mhz (1) in hsusbx, x is equal to 1, 2, or 3. submit documentation feedback timing requirements and switching characteristics 225 product preview hsusbx_clk hsusbx_stp hsusbx_dir_&_nxt hsusbx_data[7:0] data_out data_in hsu1 hsu0 hsu1 hsu4 hsu2 hsu2 hsu6 hsu3 hsu5 030-087
6.6.4.4 high-speed universal serial bus (usb) on ports 1, 2, and 3 ? 8-bit tll master mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-103. high-speed usb switching characteristics ? 12-bit tll master mode (continued) no. parameter 1.15 v unit min max t j(clk) jitter standard deviation (2) , hsusbx_tll_clk 200 ps hsu6 t d(clkl-dirv) delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid 9 ns t d(clkl-diriv) delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid 0 ns t d(clkl-nxtv) delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid 9 ns t d(clkl-nxtiv) delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid 0 ns hsu7 t d(clkl-dv) delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid 9 ns t d(clkl-div) delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid 0 ns t r(do) rise time, output signals 2 ns t f(do) fall time, output signals 2 ns (2) the jitter probability density can be approximated by a gaussian function. in hsusbx, x is equal to 1, 2, or 3. figure 6-51. high-speed usb ? 12-bit tll master mode table 6-105 and table 6-106 assume testing over the recommended operating conditions (see figure 6-52 ). table 6-104. high-speed usb timing conditions ? 8-bit tll master mode timing condition parameter value unit input conditions t r input signal rise time 2 ns t f input signal fall time 2 ns output conditions c load output load capacitance 3 pf table 6-105. high-speed usb timing requirements ? 8-bit tll master mode (1) no. parameter 1.15 v unit min max hsu2 t s(stpv-clkh) setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns hsu3 t s(clkh-stpiv) hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns hsu4 t s(datav-clkh) setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge 3 ns (1) in hsusbx, x is equal to 1, 2, or 3. timing requirements and switching characteristics 226 submit documentation feedback product preview hsusbx_tll_clk hsusbx_tll_stp hsusbx_tll_dir_&_nxt hsusbx_tll_data[7:0] data_in data_out hsu0 hsu6 hsu2 hsu3 hsu5 hsu4 hsu7 hsu7 hsu6 030-088
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-105. high-speed usb timing requirements ? 8-bit tll master mode (continued) no. parameter 1.15 v unit min max hsu5 t h(clkh-dativ) hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge ?0.8 ns table 6-106. high-speed usb switching characteristics ? 8-bit tll master mode (1) no. parameter 1.15 v unit min max hsu0 f p(clk) hsusbx_tll_clk clock frequency 60 mhz t j(clk) jitter standard deviation (2) , hsusbx_tll_clk 200 ps hsu1 t j(clk) duty cycle, hsusbx_tll_clk pulse duration (low and high) 47.6% 52.4% hsu6 t d(clkl-dirv) delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid 9 ns t d(clkl-diriv) delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid 0 ns t d(clkl-nxtv) delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid 9 ns t d(clkl-nxtiv) delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid 0 ns hsu7 t d(clkl-dv) delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid 4 ns hsu8 t d(clkl-div) delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid 0 ns t r(do) rise time, output signals 2 ns t f(do) fall time, output signals 2 ns (1) in hsusbx, x is equal to 1, 2, or 3. (2) the jitter probability density can be approximated by a gaussian function. in hsusbx, x is equal to 1, 2, or 3. figure 6-52. high-speed usb ? 8-bit tll master mode submit documentation feedback timing requirements and switching characteristics 227 product preview hsusbx_tll_clk hsusbx_tll_stp hsusbx_tll_dir_&_nxt hsusbx_tll_data[3:0] data_in data_in_(n+1) data_in_(n+2) data_out data_out_(n+1) hsu0 hsu6 hsu2 hsu3 hsu6 hsu1 hsu1 hsu4 hsu4 hsu5 hsu5 hsu7 hsu8 hsu7 030-089
6.6.5 i 2 c interface 6.6.5.1 i 2 c standard/fast-speed mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the multimaster i 2 c peripheral provides an interface between two or more devices via an i 2 c serial bus. the i 2 c controller supports the multimaster mode which allows more than one device capable of controlling the bus to be connected to it. each i 2 c device is recognized by a unique address and can operate as either transmitter or receiver, according to the function of the device. in addition to being a transmitter or receiver, a device connected to the i 2 c bus can also be considered as master or slave when performing data transfers. this data transfer is carried out via two serial bidirectional wires: an sda data line an scl clock line the following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing format. the i 2 c interface is compliant with philips i 2 c specification version 2.1. it supports standard mode (up to 100k bits/s), fast mode (up to 400k bits/s) and high-speed mode (up to 3.4mb/s) . table 6-107. i 2 c standard/fast-speed mode timings no. parameter (1) standard mode fast mode unit min max min max f scl clock frequency, i2cx_scl 100 400 khz i1 t w(sclh) pulse duration, i2cx_scl high 4 0.6 m s i2 t w(scll) pulse duration, i2cx_scl low 4.7 1.3 m s i3 t su(sdav-sclh) setup time, i2cx_sda valid before i2cx_scl active level 250 100 (2) ns i4 t h(sclh?sdav) hold time, i2cx_sda valid after i2cx_scl active level 0 (3) 3.45 (4) 0 (3) 0.9 (4) m s i5 t su(sdal-sclh) setup time, i2cx_scl high after i2cx_sda low (for a 4.7 0.6 m s start (5) condition or a repeated start condition) i6 t h(sclh?sdah) hold time, i2cx_sda low level after i2cx_scl high level 4 0.6 m s (stop condition) i7 t h(sclh?rstart) hold time, i2cx_sda low level after i2cx_scl high level (for 4 0.6 m s a repeated start condition) i8 t w(sdah) pulse duration, i2cx_sda high between stop and start 4.7 1.3 m s conditions t r(scl) rise time, i2cx_scl 1000 300 ns t f(scl) fall time, i2cx_scl 300 300 ns t r(sda) rise time, i2cx_sda 1000 300 ns t f(sda) fall time, i2cx_sda 300 300 ns cb capacitive load for each bus line 400 400 pf (1) in i2cx, x is equal to 1, 2, 3, or 4. note that i2c4 is master transmitter only. (2) a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sdav-sclh) 3 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the i2cx_scl. if such a device does stretch the low period of the i2cx_scl, it must output the next data bit to the i2cx_sda line t r(sda) max + t su(sdav-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the i2cx_scl line is released. (3) the device provides (via the i 2 c bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to bridge the undefined region of the falling edge of i2cx_scl. (4) the maximum t h(sclh-sda) has only to be met if the device does not stretch the low period of the i2cx_scl signal. (5) after this time, the first clock is generated. timing requirements and switching characteristics 228 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-53. i 2 c ? standard/fast mode submit documentation feedback timing requirements and switching characteristics 229 product preview i2cx_sda i2cx_scl start repeat stop start start i1 i2 i3 i4 i5 i6 i6 i7 i8 030-093
6.6.5.2 i 2 c high-speed mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-108. i 2 c highspeed mode timings (1) (2) no. parameter cb = 100 pf max cb = 400 pf max unit min max min max f scl clock frequency, i2cx_scl 3.4 1.7 mhz i1 t w(sclh) pulse duration, i2cx_scl high 60 (3) 120 (3) m s i2 t w(scll) pulse duration, i2cx_scl low 160 (3) 320 (3) m s i3 t su(sdav-sclh) setup time, i2cx_sda valid before i2cx_scl 10 10 ns active level i4 t h(sclh?sdav) hold time, i2cx_sda valid after i2cx_scl active 0 (2) 70 0 (2) 150 m s level i5 t su(sdal-sclh) setup time, i2cx_scl high after i2cx_sda low 160 160 m s (for a start (4) condition or a repeated start condition) i6 t h(sclh?sdah) hold time, i2cx_sda low level after i2cx_scl high 160 160 m s level (stop condition) i7 t h(sclh?rstart) hold time, i2cx_sda low level after i2cx_scl high 160 160 ns level (for a repeated start condition) t r(scl) rise time, i2cx_scl 40 80 ns t r(scl) rise time, i2cx_scl after a repeated start 80 160 ns condition and after a bit acknowledge t f(scl) fall time, i2cx_scl 40 80 ns t r(sda) rise time, i2cx_sda 80 160 ns t f(sda) fall time, i2cx_sda 80 160 ns (1) in i2cx, x is equal to 1, 2, 3, or 4. note that i2c4 is master transmitter only. (2) the device provides (via the i 2 c bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to bridge the undefined region of the falling edge of i2cx_scl. (3) hs-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t w(scll) > 2 t w(sclh) . (4) after this time, the first clock is generated. figure 6-54. i 2 c ? high-speed mode (1) (2) (3) (1) hs-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t w(scll) > 2 x t w(sclh) . (2) in i2cx, x is equal to 1, 2, 3, or 4. note that i2c4 is master transmitter only. (3) after this time, the first clock is generated. table 6-109. correspondence standard vs. ti timing references ti-omap standard-i 2 c s/f mode hs mode f scl f scl f sclh i1 t w(sclh) t high t high i2 t w(scll) t low t low i3 t su(sdav-sclh) t su;dat t su;dat i4 t h(sclh-sdav) t su;dat t su;dat i5 t su(sdal-sclh) t su;sta t su;sta i6 t h(sclh-sdah) t hd;sta t hd;sta i7 t h(sclh-rstart) t su;sto t su;sto timing requirements and switching characteristics 230 submit documentation feedback product preview i2cx_sda i2cx_scl stop start repeat i1 i2 i3 i4 i6 i5 i7 030-094
6.6.6 hdq / 1-wire interfaces 6.6.6.1 hdq protocol omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-109. correspondence standard vs. ti timing references (continued) ti-omap standard-i 2 c s/f mode hs mode i8 t w(sdah) t buf this module is intended to work with both the hdq and the 1-wire protocols. the protocols use a single wire to communicate between the master and the slave. the protocols employ an asynchronous return to 1 mechanism where, after any command, the line is pulled high. table 6-110 and table 6-111 assume testing over the recommended operating conditions (see figure 6-55 through figure 6-58 ). table 6-110. hdq timing requirements parameter description min max unit t cycd bit window 253 m s t hw1 reads 1 68 t hw0 reads 0 180 t rsps command to host respond time (1) (1) defined by software. table 6-111. hdq switching characteristics parameter description min typ max unit t b break timing 193 m s t br break recovery 63 t cych bit window 253 t dw1 sends1 (write) 1.3 t dw0 sends0 (write) 101 figure 6-55. hdq break (reset) timing figure 6-56. hdq read bit timing (data) submit documentation feedback timing requirements and switching characteristics 231 product preview hdq tb tbr 030-095 hdq thw1 thw0 tcych 030-096
6.6.6.2 1-wire protocol omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-57. hdq write bit timing (command/address or data) figure 6-58. hdq communication timing table 6-112 and table 6-113 assume testing over the recommended operating conditions (see figure 6-59 through figure 6-61 ). table 6-112. 1-wire timing requirements parameter description min max unit t pdh presence pulse delay high 68 m s t pdl presence pulse delay low 68 ? t pdh t rdv + t rel read bit-zero time 102 table 6-113. 1-wire switching characteristics parameter description min typ max unit t rstl reset time low 484 m s t rsth reset time high 484 t slot write bit cycle time 102 t low1 write bit-one time 1.3 t low0 write bit-zero time 101 t rec recovery time 134 t lowr read bit strobe time 13 figure 6-59. 1-wire break (reset) timing 232 timing requirements and switching characteristics submit documentation feedback product preview hdq tdw1 tdw0 tcycd 030-097 hdq break 0_(lsb ) 1 6 7_(msb) trsps 0_(lsb) 1 6 command _byte_written data_byte_received 030-098 1-wire trsth tpdl tpdh trtsl 030-099
6.6.7 uart irda interface 6.6.7.1 irda?receive mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-60. 1-wire read bit timing (data) figure 6-61. 1-wire write bit timing (command/address or data) the irda module can operate in three different modes: slow infrared (sir) ( 115.2 kbits/s) medium infrared (mir) (0.576 mbits/s and 1.152 mbits/s) fast infrared (fir) (4 mbits/s) for more information about this interface, see the uart/irda chapter in the omap35x technical reference manual (trm) [literature number spruf98 ]. figure 6-62. uart irda pulse parameters table 6-114. uart irda?signaling rate and pulse duration?receive mode electrical pulse duration signaling rate unit min nominal max sir 2.4 kbit/s 1.41 78.1 88.55 m s 9.6 kbit/s 1.41 19.5 22.13 m s 19.2 kbit/s 1.41 9.75 11.07 m s submit documentation feedback timing requirements and switching characteristics 233 product preview 1-wire tlowr trdv_and_ trel tslot_and_ trec 030-100 1-wire tlow1 tlow0 tslot_and_trec 030-101 030-118 pulse duration 90% 50% 10% t f 90% 50% 10% t r
6.6.7.2 irda?transmit mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-114. uart irda?signaling rate and pulse duration?receive mode (continued) electrical pulse duration signaling rate unit min nominal max 38.4 kbit/s 1.41 4.87 5.96 m s 57.6 kbit/s 1.41 3.25 4.34 m s 115.2 kbit/s 1.41 1.62 2.23 m s mir 0.576 mbit/s 297.2 416 518.8 ns 1.152 mbit/s 149.6 208 258.4 ns fir 4.0 mbit/s (single pulse) 67 125 164 ns 4.0 mbit/s (double pulse) 190 250 289 ns table 6-115. uart irda?rise and fall time?receive mode parameter max unit t r rising time, 200 ns uart3_rx_irrx t f falling time, 200 ns uart3_rx_irrx table 6-116. uart irda?signaling rate and pulse duration?transmit mode signaling rate electrical pulse duration unit min nominal max sir 2.4 kbit/s 78.1 78.1 78.1 m s 9.6 kbit/s 19.5 19.5 19.5 m s 19.2 kbit/s 9.75 9.75 9.75 m s 38.4 kbit/s 4.87 4.87 4.87 m s 57.6 kbit/s 3.25 3.25 3.25 m s 115.2 kbit/s 1.62 1.62 1.62 m s mir 0.576 mbit/s 414 416 419 ns 1.152 mbit/s 206 208 211 ns fir 4.0 mbit/s (single pulse) 123 125 128 ns 4.0 mbit/s (double pulse) 248 250 253 ns timing requirements and switching characteristics 234 submit documentation feedback product preview
6.7 removable media interfaces 6.7.1 high-speed multimedia memory card (mmc) and secure digital io card (sdio) timing 6.7.1.1 mmc/sd/sdio in sd identification mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 the mmc/sdio host controller provides an interface to high-speed and standard mmc, sd memory cards, or sdio cards. the application interface is responsible for managing transaction semantics. the mmc/sdio host controller deals with mmc/sdio protocol at transmission level, packing data, adding crc, start/end bit, and checking for syntactical correctness. there are three mmc interfaces on the omap35 15/03: mmc/sd/sdio interface 1: ? 1.8 v/3 v support ? 8 bits mmc/sd/sdio interface 2: ? 1.8 v support ? 8 bits ? 4 bits with external transceiver allowing to support 3 v peripherals. transceiver direction control signals are multiplexed with the upper four data bits. mmc/sd/sdio interface 3: ? 1.8 v support ? 8 bits table 6-118 and table 6-119 assume testing over the recommended operating conditions and electrical characteristic conditions. table 6-117. mmc/sd/sdio timing conditions ? sd identification mode timing condition parameter value unit sd identification mode input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output conditions c load output load capacitance 40 pf table 6-118. mmc/sd/sdio timing requirements ? sd identification mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max sd identification mode mmc/sd/sdio interface 1 (1.8 v io) hssd3/sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 1198.4 1198.4 ns mmc1_clk rising clock edge hssd4/sd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after 1249.2 1249.2 ns mmc1_clk rising clock edge mmc/sd/sdio interface 1 (3.0 v io) hssd3/sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 1198.4 1198.4 ns mmc1_clk rising clock edge hssd4/sd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after 1249.2 1249.2 ns mmc1_clk rising clock edge mmc/sd/sdio interface 2 (1) timing parameters are referred to output clock specified in table 6-119 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-119 . (3) corresponding figures showing timing parameters are common with other interface modes. (see sd and hs sd modes). submit documentation feedback timing requirements and switching characteristics 235 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-118. mmc/sd/sdio timing requirements ? sd identification mode (continued) no. parameter 1.15 v 1.0 v unit min max min max hssd3/sd3 t su(cmdv-clkih) setup time, mmc2_cmd valid before 1198.4 1198.4 ns mmc2_clk rising clock edge hssd4/sd4 t su(clkih-cmdiv) hold time, mmc2_cmd valid after 1249.2 1249.2 ns mmc2_clk rising clock edge mmc/sd/sdio interface 3 hssd3/sd3 t su(cmdv-clkih) setup time, mmc3_cmd valid before 1198.4 1198.4 ns mmc3_clk rising clock edge hssd4/sd4 t su(clkih-cmdiv) hold time, mmc3_cmd valid after 1249.2 1249.2 ns mmc3_clk rising clock edge table 6-119. mmc/sd/sdio switching characteristics ? sd identification mode (1) no. parameter 1.15 v 1.0 v unit min max min max sd identification mode hssd1/sd1 t c(clk) cycle time (2) , output clk period 2500 2500 ns hssd2/sd2 t w(clkh) typical pulse duration, output clk high x (3) *po (4) x (3) *po (4) ns hssd2/sd2 t w(clkl) typical pulse duration, output clk low y (5) *po (4) y (5) *po (4) ns t dc(clk) duty cycle error, output clk 125 125 ns t j(clk) jitter standard deviation (6) , output clk 200 200 ps mmc/sd/sdio interface 1 (1.8 v io) t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns hssd5/sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 6.3 2492.7 6.3 2492.7 ns mmc1_cmd transition mmc/sd/sdio interface 1 (3.0 v io) t c(clk) rise time, output clk 10 0 ns t w(clkh) fall time, output clk 10 0 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns hssd5/sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 6.3 2492.7 6.3 2492.7 ns mmc1_cmd transition mmc/sd/sdio interface 2 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns hssd5/sd5 t d(clkoh-cmd) delay time, mmc2_clk rising clock edge to 6.3 2492.7 6.3 2492.7 ns mmc2_cmd transition mmc/sd/sdio interface 3 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns (1) corresponding figures showing timing parameters are common with other interface modes (see sd and hs sd modes). (2) related with the output clk maximum and minimum frequencies programmable in i/f module. (3) the x parameter is defined as shown in table 6-120 . (4) po = output clk period in ns. (5) the y parameter is defined as shown in table 6-121 . (6) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 236 submit documentation feedback product preview
6.7.1.2 mmc/sd/sdio in high-speed mmc mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-119. mmc/sd/sdio switching characteristics ? sd identification mode (continued) no. parameter 1.15 v 1.0 v unit min max min max t dc(clk) fall time, output data 10 10 ns hssd5/sd5 t d(clkoh-cmd) delay time, mmc3_clk rising clock edge to 6.3 2492.7 6.3 2492.7 ns mmc3_cmd transition table 6-120. x parameter clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd table 6-121. y parameter clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd for details about clock division factor clkd, see the omap35x technical reference manual (trm) [literature number spruf98 ]. table 6-123 and table 6-124 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-63 and figure 6-64 ). table 6-122. mmc/sd/sdio timing conditions ? high-speed mmc mode timing condition parameter value unit high-speed mmc mode input conditions t r input signal rise time 3 ns t f input signal fall time 3 ns output conditions c load output load capacitance 30 pf table 6-123. mmc/sd/sdio timing requirements ? high-speed mmc mode (1) (2) (3) (4) no. parameter 1.15 v 1.0 v unit min max min max high-speed mmc mode mmc/sd/sdio interface 1 (1.8 v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk 5.6 26 ns rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc1_datx valid before mmc1_clk 5.6 26 ns rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 1 (3.0 v io) (1) timing parameters are referred to output clock specified in table 6-124 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-124 . (3) corresponding figures showing timing parameters are common with standard mmc mode (see figure 6-63 and figure 6-64 ) (4) in datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. submit documentation feedback timing requirements and switching characteristics 237 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-123. mmc/sd/sdio timing requirements ? high-speed mmc mode (continued) no. parameter 1.15 v 1.0 v unit min max min max mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk 5.6 26 ns rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc1_datx valid before mmc1_clk 5.6 26 ns rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 2 mmc3 t su(cmdv-clkih) setup time, mmc2_cmd valid before mmc2_clk 5.6 26 ns rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc2_cmd valid after mmc2_clk 2.3 1.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc2_datx valid before mmc2_clk 5.6 26 ns rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc2_datx valid after mmc2_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 3 mmc3 t su(cmdv-clkih) setup time, mmc3_cmd valid before mmc3_clk 5.6 26 ns rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc3_cmd valid after mmc3_clk 2.3 1.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc3_datx valid before mmc3_clk 5.6 26 ns rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc3_datx valid after mmc3_clk 2.3 1.9 ns rising clock edge table 6-124. mmc/sd/sdio switching characteristics ? high-speed mmc mode (1) n o. parameter 1.15 v 1.0 v unit min max min max high-speed mmc mode mmc1 t c(clk) cycle time (2) , output clk period 20.8 41.7 ns mmc2 t w(clkh) typical pulse duration, output clk high x (3) *po (4) x (3) *po (4) ns mmc2 t w(clkl) typical pulse duration, output clk low y (5) *po (4) y (5) *po (4) ns t dc(clk) duty cycle error, output clk 1041.7 2083.3 ps t j(clk) jitter standard deviation (6) , output clk 200 200 ps mmc/sd/sdio interface 1 (1.8 v io) t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_cmd transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_datx transition mmc/sd/sdio interface 1 (3.0 v io) (1) in datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. (2) related with the output clk maximum and minimum frequencies programmable in i/f module. (3) the x parameter is defined as shown in table 6-125 . (4) po = output clk period in ns. (5) the y parameter is defined as shown in table 6-126 . (6) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 238 submit documentation feedback product preview
6.7.1.3 mmc/sd/sdio in standard mmc mode and mmc identification mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-124. mmc/sd/sdio switching characteristics ? high-speed mmc mode (continued) n o. parameter 1.15 v 1.0 v unit min max min max t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_cmd transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_datx transition mmc/sd/sdio interface 2 t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc2_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc2_cmd transition mmc6 t d(clkoh-datx) delay time, mmc2_clk rising clock edge to 3.7 16.5 4.1 36.9 ns mmc2_datx transition mmc/sd/sdio interface 3 t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns mmc5 t d(clkoh-cmd) delay time, mmc3_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc3_cmd transition mmc6 t d(clkoh-datx) delay time, mmc3_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc3_datx transition table 6-125. x parameter clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd table 6-126. y parameter clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd for details about clock division factor clkd, see the omap35x technical reference manual (trm) [literature number spruf98 ]. table 6-128 and table 6-129 assume testing over the recommended operating conditions and electrical characteristic conditions. table 6-127. mmc/sd/sdio timing conditions ? standard mmc mode and mmc identification mode timing condition parameter value unit standard mmc mode and mmc identification mode input conditions submit documentation feedback timing requirements and switching characteristics 239 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-127. mmc/sd/sdio timing conditions ? standard mmc mode and mmc identification mode (continued) timing condition parameter value unit t r input signal rise time 10 ns t f input signal fall time 10 ns output conditions c load output load capacitance 30 pf timing requirements and switching characteristics 240 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-128. mmc/sd/sdio timing requirements ? standard mmc mode and mmc identification mode (1) (2) no. parameter 1.15 v 1.0 v unit min max min max standard mmc mode and mmc identification mode mmc/sd/sdio interface 1 (1.8 v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 13.6 65.7 ns mmc1_clk rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 8.9 8.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc1_datx valid before 13.6 65.7 ns mmc1_clk rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 8.9 8.9 ns rising clock edge mmc/sd/sdio interface 1 (3.0 v io) mmc3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 13.6 65.7 ns mmc1_clk rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 8.9 8.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc1_datx valid before 13.6 65.7 ns mmc1_clk rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 8.9 8.9 ns rising clock edge mmc/sd/sdio interface 2 mmc3 t su(cmdv-clkih) setup time, mmc2_cmd valid before 13.6 65.7 ns mmc2_clk rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc2_cmd valid after mmc2_clk 8.9 8.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc2_datx valid before 13.6 65.7 ns mmc2_clk rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc2_datx valid after mmc2_clk 8.9 8.9 ns rising clock edge mmc/sd/sdio interface 3 mmc3 t su(cmdv-clkih) setup time, mmc3_cmd valid before 13.6 65.7 ns mmc3_clk rising clock edge mmc4 t su(clkih-cmdiv) hold time, mmc3_cmd valid after mmc3_clk 8.9 8.9 ns rising clock edge mmc7 t su(datxv-clkih) setup time, mmc3_datx valid before 13.6 65.7 ns mmc3_clk rising clock edge mmc8 t su(clkih-datxiv) hold time, mmc3_datx valid after mmc3_clk 8.9 8.9 ns rising clock edge (1) timing parameters are referred to output clock specified in table 6-129 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-129 . table 6-129. mmc/sd/sdio switching characteristics ? standard mmc mode and mmc identification mode no. parameter 1.15 v 1.0 v unit min max min max mmc identification mode mmc1 t c(clk) cycle time (1) , output clk period 2500 2500 ns mmc2 t w(clkh) typical pulse duration, output clk high x (2) *po (3) x (2) *po (3) ns mmc2 t w(clkl) typical pulse duration, output clk low y*po (3) y*po (3) ns (1) related with the output clk maximum and minimum frequencies programmable in i/f module. (2) the x parameter is defined as shown in table 6-130 . (3) po = output clk period in ns. submit documentation feedback timing requirements and switching characteristics 241 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-129. mmc/sd/sdio switching characteristics ? standard mmc mode and mmc identification mode (continued) no. parameter 1.15 v 1.0 v unit min max min max t dc(clk) duty cycle error, output clk 125 125 ns t j(clk) jitter standard deviation (4) , output clk 200 200 ps standard mmc mode mmc1 t c(clk) cycle time (1) , output clk period 52.1 104.2 ns mmc2 t w(clkh) typical pulse duration, output clk high x (2) *po (3) x (2) *po (3) ns mmc2 t w(clkl) typical pulse duration, output clk low y*po (3) y*po (3) ns t dc(clk) duty cycle error, output clk 2604.2 5208.3 ps t j(clk) jitter standard deviation (4) , output clk 200 200 ps mmc/sd/sdio interface 1 (1.8 v io) t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc1_cmd transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc1_datx transition mmc/sd/sdio interface 1 (3.0 v io) t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc1_cmd transition mmc6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc1_datx transition mmc/sd/sdio interface 2 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc2_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc2_cmd transition mmc6 t d(clkoh-datx) delay time, mmc2_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc2_datx transition mmc/sd/sdio interface 3 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns mmc5 t d(clkoh-cmd) delay time, mmc3_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc3_cmd transition mmc6 t d(clkoh-datx) delay time, mmc3_clk rising clock edge to 4.3 47.8 4.3 99.9 ns mmc3_datx transition (4) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 242 submit documentation feedback product preview
6.7.1.4 mmc/sd/sdio in high-speed sd mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-130. x parameter clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd table 6-131. y parameter clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd for details about clock division factor clkd, see the omap35x technical reference manual (trm) [literature number spruf98 ]. in mmcx, x is equal to 1, 2, or 3. figure 6-63. mmc/sd/sdio ? high-speed and standard mmc modes ? data/command receive in mmcx, x is equal to 1, 2, or 3. figure 6-64. mmc/sd/sdio ? high-speed and standard mmc modes ? data/command transmit table 6-133 and table 6-134 assume testing over the recommended operating conditions and electrical characteristic conditions. table 6-132. mmc/sd/sdio timing conditions ? high-speed sd mode timing condition parameter value unit high-speed sd mode input conditions t r input signal rise time 3 ns t f input signal fall time 3 ns output conditions c load output load capacitance 40 pf submit documentation feedback timing requirements and switching characteristics 243 product preview mmcx_clk mmcx_cmd mmcx_dat[3:0] mmc3 mmc7 mmc4 mmc8 mmc1 mmc2 030-104 mmcx_clk mmcx_cmd mmcx_dat[3:0] mmc5 mmc5 mmc6 mmc6 mmc1 mmc2 030-105
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-133. mmc/sd/sdio timing requirements ? high-speed sd mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max high-speed sd mode mmc/sd/sdio interface 1 (1.8 v io) hssd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 5.6 26 ns mmc1_clk rising clock edge hssd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge hssd7 t su(datxv-clkih) setup time, mmc1_datx valid before 5.6 26 ns mmc1_clk rising clock edge hssd8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 1 (3.0 v io) hssd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before 5.6 26 ns mmc1_clk rising clock edge hssd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge hssd7 t su(datxv-clkih) setup time, mmc1_datx valid before 5.6 26 ns mmc1_clk rising clock edge hssd8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 2 hssd3 t su(cmdv-clkih) setup time, mmc2_cmd valid before 5.6 26 ns mmc2_clk rising clock edge hssd4 t su(clkih-cmdiv) hold time, mmc2_cmd valid after mmc2_clk 2.3 1.9 ns rising clock edge hssd7 t su(datxv-clkih) setup time, mmc2_datx valid before 5.6 26 ns mmc2_clk rising clock edge hssd8 t su(clkih-datxiv) hold time, mmc2_datx valid after mmc2_clk 2.3 1.9 ns rising clock edge mmc/sd/sdio interface 3 hssd3 t su(cmdv-clkih) setup time, mmc3_cmd valid before 5.6 26 ns mmc3_clk rising clock edge hssd4 t su(clkih-cmdiv) hold time, mmc3_cmd valid after mmc3_clk 2.3 1.9 ns rising clock edge hssd7 t su(datxv-clkih) setup time, mmc3_datx valid before 5.6 26 ns mmc3_clk rising clock edge hssd8 t su(clkih-datxiv) hold time, mmc3_datx valid after mmc3_clk 2.3 1.9 ns rising clock edge (1) timing parameters are referred to output clock specified in table 6-134 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-134 . (3) in datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. table 6-134. mmc/sd/sdio switching characteristics ? high-speed sd mode no. parameter 1.15 v 1.0 v unit min max min max high-speed sd mode hssd1 t c(clk) cycle time (1) , output clk period 20.8 41.7 ns hssd2 t w(clkh) typical pulse duration, output clk high x (2) *po (3) x (2) *po (3) ns hssd2 t w(clkl) typical pulse duration, output clk low y (4) *po (3) y (4) *po (3) ns (1) related with the output clk maximum and minimum frequencies programmable in i/f module. (2) the x parameter is defined as shown in table 6-135 . (3) po = output clk period in ns. (4) the y parameter is defined as shown in table 6-136 . timing requirements and switching characteristics 244 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-134. mmc/sd/sdio switching characteristics ? high-speed sd mode (continued) no. parameter 1.15 v 1.0 v unit min max min max t dc(clk) duty cycle error, output clk 1041.7 2083.3 ps t j(clk) jitter standard deviation (5) , output clk 200 200 ps mmc/sd/sdio interface 1 (1.8 v io) t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_cmd transition hssd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_datx transition mmc/sd/sdio interface 1 (3.0 v io) t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_cmd transition hssd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_datx transition mmc/sd/sdio interface 2 t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc2_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc2_cmd transition hssd6 t d(clkoh-datx) delay time, mmc2_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc2_datx transition mmc/sd/sdio interface 3 t c(clk) rise time, output clk 3 3 ns t w(clkh) fall time, output clk 3 3 ns t w(clkl) rise time, output data 3 3 ns t dc(clk) fall time, output data 3 3 ns hssd5 t d(clkoh-cmd) delay time, mmc3_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc3_cmd transition hssd6 t d(clkoh-datx) delay time, mmc3_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc3_datx transition (5) the jitter probability density can be approximated by a gaussian function. table 6-135. x parameters clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd submit documentation feedback timing requirements and switching characteristics 245 product preview
6.7.1.5 mmc/sd/sdio in standard sd mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-136. y parameters clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd for details about clock division factor clkd, see the omap35x technical reference manual (trm) [literature number spruf98 ]. in mmcx, x is equal to 1, 2, or 3. figure 6-65. mmc/sd/sdio ? high-speed sd mode ? data/command receive in mmcx, x is equal to 1, 2, or 3. figure 6-66. mmc/sd/sdio ? high-speed sd mode ? data/command transmit table 6-138 and table 6-139 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-67 ). table 6-137. mmc/sd/sdio timing conditions ? standard sd mode timing condition parameter value unit standard sd mode input conditions t r input signal rise time 10 ns t f input signal fall time 10 ns output conditions c load output load capacitance 40 pf timing requirements and switching characteristics 246 submit documentation feedback product preview mmcx_clk mmcx_cmd mmcx_dat[3:0] hssd3 hssd7 hssd4 hssd8 hssd1 hssd2 030-106 mmcx_clk mmcx_cmd mmcx_dat[3:0] hssd5 hssd5 hssd6 hssd6 hssd1 hssd2 030-107
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-138. mmc/sd/sdio timing requirements ? standard sd mode (1) (2) (3) no. parameter 1.15 v 1.0 v unit min max min max standard sd mode mmc/sd/sdio interface 1 (1.8 v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk 6.2 47.7 ns rising clock edge sd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 19.4 19.2 ns rising clock edge sd7 t su(datxv-clkih) setup time, mmc1_datx valid before mmc1_clk 6.2 47.7 ns rising clock edge sd8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 19.4 19.2 ns rising clock edge mmc/sd/sdio interface 1 (3.0 v io) sd3 t su(cmdv-clkih) setup time, mmc1_cmd valid before mmc1_clk 6.2 47.7 ns rising clock edge sd4 t su(clkih-cmdiv) hold time, mmc1_cmd valid after mmc1_clk 19.4 19.2 ns rising clock edge sd7 t su(datxv-clkih) setup time, mmc1_datx valid before mmc1_clk 6.2 47.7 ns rising clock edge sd8 t su(clkih-datxiv) hold time, mmc1_datx valid after mmc1_clk 19.4 19.2 ns rising clock edge mmc/sd/sdio interface 2 sd3 t su(cmdv-clkih) setup time, mmc2_cmd valid before mmc2_clk 6.2 47.7 ns rising clock edge sd4 t su(clkih-cmdiv) hold time, mmc2_cmd valid after mmc2_clk 19.4 19.2 ns rising clock edge sd7 t su(datxv-clkih) setup time, mmc2_datx valid before mmc2_clk 6.2 47.7 ns rising clock edge sd8 t su(clkih-datxiv) hold time, mmc2_datx valid after mmc2_clk 19.4 19.2 ns rising clock edge mmc/sd/sdio interface 3 sd3 t su(cmdv-clkih) setup time, mmc3_cmd valid before mmc3_clk 6.2 47.7 ns rising clock edge sd4 t su(clkih-cmdiv) hold time, mmc3_cmd valid after mmc3_clk 19.4 19.2 ns rising clock edge sd7 t su(datxv-clkih) setup time, mmc3_datx valid before mmc3_clk 6.2 47.7 ns rising clock edge sd8 t su(clkih-datxiv) hold time, mmc3_datx valid after mmc3_clk 19.4 19.2 ns rising clock edge (1) timing parameters are referred to output clock specified in table 6-139 . (2) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified in table 6-139 . (3) in datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. table 6-139. mmc/sd/sdio switching characteristics ? standard sd mode no. parameter 1.15 v 1.0 v unit min max min max standard sd mode sd1 t c(clk) cycle time (1) , output clk period 41.7 83.3 ns sd2 t w(clkh) typical pulse duration, output clk high x (2) *po (3) x (2) *po (3) ns sd2 t w(clkl) typical pulse duration, output clk low y (4) *po (3) y (4) *po (3) ns t dc(clk) duty cycle error, output clk 2083.3 4166.7 ps (1) related with the output clk maximum and minimum frequencies programmable in i/f module. (2) the x parameter is defined as shown in table 6-140 . (3) po = output clk period in ns. (4) the y parameter is defined as shown in table 6-141 . submit documentation feedback timing requirements and switching characteristics 247 product preview
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-139. mmc/sd/sdio switching characteristics ? standard sd mode (continued) no. parameter 1.15 v 1.0 v unit min max min max t j(clk) jitter standard deviation (5) , output clk 200 200 ps mmc/sd/sdio interface 1 (1.8 v io) t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc1_cmd transition sd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc1_datx transition mmc/sd/sdio interface 1 (3.0 v io) t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc1_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc1_cmd transition sd6 t d(clkoh-datx) delay time, mmc1_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc1_datx transition mmc/sd/sdio interface 2 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc2_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc2_cmd transition sd6 t d(clkoh-datx) delay time, mmc2_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc2_datx transition mmc/sd/sdio interface 3 t c(clk) rise time, output clk 10 10 ns t w(clkh) fall time, output clk 10 10 ns t w(clkl) rise time, output data 10 10 ns t dc(clk) fall time, output data 10 10 ns sd5 t d(clkoh-cmd) delay time, mmc3_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc3_cmd transition sd6 t d(clkoh-datx) delay time, mmc3_clk rising clock edge to 6.1 35.5 6.3 77 ns mmc3_datx transition (5) the jitter probability density can be approximated by a gaussian function. table 6-140. x parameter clkd x 1 or even 0.5 odd (trunk[clkd/2]+1)/clkd table 6-141. y parameter clkd y 1 or even 0.5 odd (trunk[clkd/2])/clkd timing requirements and switching characteristics 248 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 for details about clock division factor clkd, see the omap35x technical reference manual (trm) [literature number spruf98 ]. in mmcx, x is equal to 1, 2, or 3. figure 6-67. mmc/sd/sdio ? standard sd mode ? data/command receive in mmcx, x is equal to 1, 2, or 3. figure 6-68. mmc/sd/sdio ? standard sd mode ? data/command transmit submit documentation feedback timing requirements and switching characteristics 249 product preview mmcx_clk mmcx_cmd mmcx_dat[3:0] sd3 sd7 sd4 sd8 sd1 sd2 030-108 mmcx_clk mmcx_cmd mmcx_dat[3:0] sd1 sd2 sd5 sd6 sd5 sd6 030-109
6.8 test interfaces 6.8.1 embedded trace macro interface (etm) 6.8.2 system debug trace interface (sdti) 6.8.2.1 system debug trace interface in dual-edge mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com the emulation and trace interfaces allow tracing activities of the following cpus: arm1136jf-stm through an embedded trace macro-cell (etm11) dedicated to enable real-time trace of the arm subsystem operations and a serial debug trace interface (sdti) all processors can be emulated via jtag ports. table 6-142 assumes testing over the recommended operating conditions (see figure 6-69 ). table 6-142. embedded trace macro interface switching characteristics (1) no. parameter 1.15 v unit min max f 1/t c(clk) frequency, etk_clk 166 mhz etm0 t c(clk) cycle time (2) , etk_clk 6 ns etm1 t w(clk) clock pulse width, etk_clk 2.7 ns etm2 t d(clk-ctl) delay time, etk_clk clock edge to etk_ctl transition ?0.5 0.5 ns etm3 t d(clk-d) delay time, etk_clk clock high to etk_d[15:0] transition ?0.5 0.5 ns (1) the capacitive load is equivalent to 25 pf. (2) cycle time is given by considering a jitter of 5%. figure 6-69. embedded trace macro interface the system debug trace interface (sdti) module provides real-time software tracing functionality to the omap35 15/03 device. the trace interface has four trace data pins and a trace clock pin. this interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can be also configured in single edge mode where data are available on falling edge of sdti_clk. serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data there is no trace clock. table 6-144 assumes testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-70 ). table 6-143. system debug trace interface timing conditions ? dual-edge mode timing condition parameter value unit output conditions c load output load capacitance 25 pf timing requirements and switching characteristics 250 submit documentation feedback product preview etk_clk etk_ctl etk_d[15:0] etm0 etm2 etm3 etm2 etm1 etm3 030-110
6.8.2.2 system debug trace interface in single-edge mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-144. system debug trace interface switching characteristics ? dual-edge mode no. parameter 1.15 v 1.0 v unit min max min max sd1 t c(clk) cycle time, sdti_clk period 29 29 ns sd2 t w(clk) typical pulse duration, sdti_clk high or low 0.5*p (1) 0.5*p (1) ns t dc(clk) duty cycle error, sdti_clk ?1.2 1.2 ?1.2 1.2 ns t r(clk) rise time, sdti_clk 5 5 ns t f(clk) fall time, sdti_clk 5 5 ns sd3 t d(clk-txd) delay time, sdti_clk multiplexing mode on etk pins 2.3 10.9 2.3 10.9 ns transition to sdti_txd[3:0] multiplexing mode on 2.3 13.9 2.3 13.9 transition jtag_emu pins t r(clk) rise time, sdti_txd[3:0] 5 5 ns t f(clk) fall time, sdti_txd[3:0] 5 5 ns (1) p = sdti_clk clock period figure 6-70. system debug trace interface ? dual-edge mode table 6-146 assumes testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-71 ). table 6-145. system debug trace interface timing conditions ? single-edge mode timing condition parameter value unit output conditions c load output load capacitance 25 pf table 6-146. system debug trace interface switching characteristics ? single-edge mode no. parameter 1.15 v 1.0 v unit min max min max sd1 t c(clk) cycle time, sdti_clk period 29 29 ns sd2 t w(clk) typical pulse duration, sdti_clk high or low 0.5*p (1) 0.5*p (1) ns t dc(clk) duty cycle error, sdti_clk ?1.2 1.2 ?1.2 1.2 ns t r(clk) rise time, sdti_clk 5 5 ns t f(clk) fall time, sdti_clk 5 5 ns sd3 t d(clk-txd) delay time, sdti_clk multiplexing mode on etk pins 2.3 26.5 2.3 26.5 ns transition to sdti_txd[3:0] multiplexing mode on jtag_emu 2.3 33.2 2.3 33.2 transition pins t r(clk) rise time, sdti_txd[3:0] 5 5 ns t f(clk) fall time, sdti_txd[3:0] 5 5 ns (1) p = sdti_clk clock period. submit documentation feedback timing requirements and switching characteristics 251 product preview sdti_clk sdti_txd[3:0] header header ad[7:4] ad[3:0] da[15:12] da[11:8] da[7:4] da[3:0] sd1 sd2 sd3 sd3 030-111
6.8.3 jtag interfaces 6.8.3.1 jtag ? free running clock mode omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com figure 6-71. system debug trace interface ? single-edge mode omap35 15/03 jtag tap controller handles standard ieee jtag interfaces. the following sections define the timing requirements for several tools used to test the omap35 15/03 processors as: free running clock tool, like xds560 and xds510 tools adaptive clock tool, like realview? ice tool and lauterbach? tool table 6-148 and table 6-149 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-72 ). table 6-147. jtag timing conditions ? free running clock mode timing condition parameter value unit input conditions t r input signal rise time 5 ns t f input signal fall time 5 ns output conditions c load output load capacitance 30 pf table 6-148. jtag timing requirements ? free running clock mode (1) no. parameter 1.15 v 1.0 v unit min max min max jt4 t c(tck) cycle time (2) , jtag_tck period 25 33 ns jt5 t w(tckl) typical pulse duration, jtag_tck low 0.5*p (3) 0.5*p (3) ns jt6 t w(tckh) typical pulse duration, jtag_tck high 0.5*p (3) 0.5*p (3) ns t dc(tck) duty cycle error, jtag_tck ?1250 1250 ?1667 1667 ps t j(tck) cycle jitter (4) , jtag_tck ?1250 1250 ?1667 1667 ps jt7 t su(tdiv-rtckh) setup time, jtag_tdi valid before jtag_rtck high 1.8 1.8 ns jt8 t h(tdiv-rtckh) hold time, jtag_tdi valid after jtag_rtck high 0.7 1 ns jt9 t su(tmsv-rtckh) setup time, jtag_tms valid before jtag_rtck high 1.8 1.8 ns jt10 t h(tmsv-rtckh) hold time, jtag_tms valid after jtag_rtck high 0.7 1 ns jt12 t su(emuxv-rtckh) setup time, jtag_emux (5) valid before jtag_rtck 14.6 19.8 ns high jt13 t h(emuxv-rtckh) hold time,jtag_emux (5) valid after jtag_rtck high 2 2.7 ns (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the jtag module. (3) p = jtag _tck period in ns. (4) maximum cycle jitter supported by jtag _tck input clock. (5) x = 0 to 1 252 timing requirements and switching characteristics submit documentation feedback product preview sdti_clk sdti_txd[3:0] header header ad[7:4] ad[3:0] da[15:12] da[11:8] da[7:4] da[3:0] sd1 sd2 sd3 sd3 030-112
6.8.3.2 jtag ? adaptive clock mode omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 table 6-149. jtag switching characteristics ? free running clock mode no. parameter 1.15 v 1.0 v unit min max min max jt1 t c(rtck) cycle time (1) , jtag_rtck period 25 33 ns jt2 t w(rtckl) typical pulse duration, jtag_rtck low 0.5*po (2) 0.5*po (2) ns jt3 t w(rtckh) typical pulse duration, jtag_rtck high 0.5*po (2) 0.5*po (2) ns t dc(rtck) duty cycle error, jtag_rtck ?1250 1250 ?1667 1667 ps t j(rtck) jitter standard deviation (3) , jtag_rtck 33.3 33.3 ps t r(rtck) rise time, jtag_rtck 4 4 ns t f(rtck) fall time, jtag_rtck 4 4 ns jt11 t d(rtckl-tdov) delay time, jtag_rtck low to jtag_tdo valid ?5.8 5.8 ?7.9 7.9 ns t r(tdo) rise time, jtag_tdo 4 4 ns t f(tdo) fall time, jtag_tdo 4 4 ns jt14 t d(rtckh-emuxv) delay time, jtag_rtck high to ,jtag_emux (4) valid 2.7 15.1 2.7 20.4 ns t r(emux) rise time, jtag_emux (4) 6 6 ns t f(emux) fall time, jtag_emux (4) 6 6 ns (1) related with the jtag_rtck maximum frequency. (2) po = jtag _rtck period in ns. (3) the jitter probability density can be approximated by a gaussian function. (4) x = 0 to 1 in jtag_emux, x is equal to 0 to 1. figure 6-72. jtag interface timing ? free running clock mode table 6-151 and table 6-152 assume testing over the recommended operating conditions and electrical characteristic conditions (see figure 6-73 ): table 6-150. jtag timing conditions ? adaptive clock mode timing condition parameter value unit input conditions t r input signal rise time 5 ns submit documentation feedback timing requirements and switching characteristics 253 product preview jtag_tck jtag_rtck jtag_tdi jtag_tms jtag_emux(in) jtag_tdo jtag_emux(out) jt7 jt11 jt1 jt2 jt3 jt8 jt10 jt9 jt4 jt5 jt6 jt12 jt13 jt14 030-113
omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 6-150. jtag timing conditions ? adaptive clock mode (continued) timing condition parameter value unit t f input signal fall time 5 ns output conditions c load output load capacitance 30 pf table 6-151. jtag timing requirements ? adaptive clock mode (1) no. parameter 1.15 v 1.0 v unit min max min max ja4 t c(tck) cycle time (2) , jtag_tck period 50 50 ns ja5 t w(tckl) typical pulse duration, jtag_tck low 0.5*p (3) 0.5*p (3) ns ja6 t w(tckh) typical pulse duration, jtag_tck high 0.5*p (3) 0.5*p (3) ns t dc(lclk) duty cycle error, jtag_tck ?2500 2500 ?2500 2500 ps t j(lclk) cycle jitter (4) , jtag_tck ?1500 1500 ?1500 1500 ps ja7 t su(tdiv-tckh) setup time, jtag_tdi valid before jtag_tck high 13.8 13.8 ns ja8 t h(tdiv-tckh) hold time, jtag_tdi valid after jtag_tck high 13.8 13.8 ns ja9 t su(tmsv-tckh) setup time, jtag_tms valid before jtag_tck high 13.8 13.8 ns ja10 t h(tmsv-tckh) hold time, jtag_tms valid after jtag_tck high 13.8 13.8 ns (1) the timing requirements are assured for the cycle jitter and duty cycle error conditions specified. (2) related with the input maximum frequency supported by the jtag module. (3) p = jtag _tck period in ns. (4) maximum cycle jitter supported by jtag _tck input clock. table 6-152. jtag switching characteristics ? adaptive clock mode no. parameter 1.15 v 1.0 v unit min max min max ja1 t c(rtck) cycle time (1) , jtag_rtck period 50 50 ns ja2 t w(rtckl) typical pulse duration, jtag_rtck low 0.5*po (2) 0.5*po (2) ns ja3 t w(rtckh) typical pulse duration, jtag_rtck high 0.5*po (2) 0.5*po (2) ns t dc(rtck) duty cycle error, jtag_rtck ?2500 2500 ?2500 2500 ps t j(rtck) jitter standard deviation (3) , jtag_rtck 33.3 33.3 ps t r(rtck) rise time, jtag_rtck 4 4 ns t f(rtck) fall time, jtag_rtck 4 4 ns ja11 t d(rtckl-tdov) delay time, jtag_rtck low to jtag_tdo valid ?14.6 14.6 ?14.6 14.6 ns t r(tdo) rise time, jtag_tdo, 4 4 ns t f(tdo) fall time, jtag_tdo 4 4 ns (1) related with the jtag _rtck maximum frequency programmable. (2) po = jtag _rtck period in ns. (3) the jitter probability density can be approximated by a gaussian function. timing requirements and switching characteristics 254 submit documentation feedback product preview
omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 figure 6-73. jtag interface timing ? adaptive clock mode submit documentation feedback timing requirements and switching characteristics 255 product preview jtag_tck jtag_tdi jtag_tmsjtag_rtck jtag_tdo ja1 ja2 ja3 ja4 ja5 ja6 ja7 ja8 ja10 ja9 ja11 030-114
7 package characteristics 7.1 package thermal resistance 7.2 device support 7.2.1 development support (tbd) 7.2.2 device and development-support tool nomenclature omap35 15/03 applications processor sprs505b ? february 2008 ? revised july 2008 www.ti.com table 7-1 provides the thermal resistance characteristics for the recommended package types used on the omap35 15/03 applications processor. table 7-1. omap35 15/03 thermal resistance characteristics (1) (2) package power (w) r q ja ( c/w) r q jb ( c/w) r q jc ( c/w) board type omap35 15/03 tbd 24.46 10.94 0.01 2s2p (3) (cbb pkg.) omap35 15/03 tbd tbd tbd tbd tbd (cbc pkg.) omap35 15/03 tbd tbd tbd tbd tbd (cus pkg.) (1) not applicable since the pop package has a memory package on top, no heat sink can be used. (tbd) (2) r q ja (theta-ja) = thermal resistance junction-to-ambient, c/w r q jb (theta-jb) = thermal resistance junction-to-board, c/w r q jc (theta-jc) = thermal resistance junction-to-case, c/w (3) the board types are defined by jedec (reference jedec standard jesd51-9, test board for area array surface mount package thermal measurements). tbd to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all omap ? processors and support tools. each omap device has one of three prefixes: x, p, or null (no prefix). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmdx) through fully qualified production devices/tools (tmds). device development evolutionary flow: x experimental device that is not necessarily representative of the final device?s electrical specifications and may not use production assembly flow. (tmx definition) p prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. (tmp definition) null production version of the silicon die that is fully qualified. (tms definition) support tool development evolutionary flow: tmdx development support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ?developmental product is intended for internal evaluation purposes.? production devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. package characteristics 256 submit documentation feedback product preview
7.2.3 documentation support 7.2.3.1 related documentation from texas instruments 7.2.3.2 related documentation from other sources omap35 15/03 applications processor www.ti.com sprs505b ? february 2008 ? revised july 2008 predictions show that prototype devices (x or p), have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. for additional description of the device nomenclature markings, see the omap35x applications processor silicon errata (literature number sprz278 ). figure 7-1. device nomenclature the following documents describe the omap35 15/03 applications processor. copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com . the current documentation that describes the omap35 15/03 applications processor, related peripherals, and other technical collateral, is available in the product folder at: www.ti.com . spruf98 omap35x technical reference manual. collection of documents providing detailed information on the omap3 architecture including power, reset, and clock control, interrupts, memory map, and switch fabric interconnect. detailed information on the microprocessor unit (mpu) subsystem, the image, video, and audio (iva2.2) subsystem, as well a functional description of the peripherals supported on omap35x devices is also included. spru889 high-speed dsp systems design reference guide. provides recommendations for meeting the many challenges of high-speed dsp system design. these recommendations include information about dsp audio, video, and communications systems for the c5000 and c6000 dsp platforms. the following documents are related to the omap35 15/03 applications processor. copies of these documents can be obtained directly from the internet or from your texas instruments representative. cortex?-a8 technical reference manual. this is the technical reference manual for the cortex-a8 processor. a copy of this document can be obtained via the internet at http://infocenter.arm.com . please see the omap35x applications processor silicon errata (literature number sprz278 ) to determine the revision of the cortex-a8 core used on your device. arm core cortextm-a8 (at400/at401) errata notice. provides a list of advisories for the different revisions of the cortex-a8 processor. contact your ti representative for a copy of this document. please see the omap35x applications processor silicon errata (literature number sprz278 ) to determine the revision of the cortex-a8 core used on your device. submit documentation feedback package characteristics 257 product preview prefix x omap3530 b x = experimental device p = prototype device blank= production device device package type cbb = 515 pin pbga cbc = 515 pin s-pbga cus = 423 pin pbga silicon revision cbb ( ) 600 blank = 0 c to 90 c (commercial temperature) a = -40 c to 105 c (extended temperature) 600 = 600 mhz cortex - a8
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) xOMAP3503bcbb active fcbga cbb 515 168 tbd call ti call ti xOMAP3503bcus active fcbga cus 423 90 tbd call ti call ti xomap3515bcbb active fcbga cbb 515 168 tbd call ti call ti xomap3515bcus active fcbga cus 423 90 tbd call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 8-aug-2008 addendum-page 1

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